sdrv_pinctrl.h

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#ifndef SDRV_PINCTRL_H_
#define SDRV_PINCTRL_H_
 
#include <types.h>
#include <sdrv_common.h>
 
/*
 * Use pinctrl.h for different parts, located in
 * SSDK_PATH/devices/E3xxx/include
 *
 * note: use macro defined in pinctrl.h when call PINCTRL/GPIO api.
 */
#include <pinctrl.h>
 
struct sdrv_gpio;
 
enum sdrv_pinctrl_error
{
    SDRV_PINCTRL_BAD_PIN = SDRV_ERROR_STATUS(SDRV_STATUS_GROUP_PINCTRL, 1),   /* PINCTRL Pin Index Wrong. */
    SDRV_PINCTRL_CTRL_NULL = SDRV_ERROR_STATUS(SDRV_STATUS_GROUP_PINCTRL, 2), /* PINCTRL Controller is NULL. */
};
 
typedef struct sdrv_input_select_t {
    uint32_t  pin    : 16;
    uint32_t  mux    : 4;
    uint32_t  offset : 16;
    uint32_t  value  : 4;
    paddr_t   base;
} sdrv_input_select_t;
 
typedef struct sdrv_pinctrl {
    paddr_t base;
    uint32_t pad_offset;
    uint32_t mux_offset;
    uint32_t pin_start;
    uint32_t pin_num;
    uint32_t disp_mux_base;
 
    uint32_t input_select_size;
    const sdrv_input_select_t *input_select;
} sdrv_pinctrl_t;
 
typedef enum pin_mux {
    PIN_MUX_ALT0  = 0U,     
    PIN_MUX_ALT1  = 1U,     
    PIN_MUX_ALT2  = 2U,     
    PIN_MUX_ALT3  = 3U,     
    PIN_MUX_ALT4  = 4U,     
    PIN_MUX_ALT5  = 5U,     
    PIN_MUX_ALT6  = 6U,     
    PIN_MUX_ALT7  = 7U,     
    PIN_MUX_ALT8  = 8U,     
    PIN_MUX_ALT9  = 9U,     
} pin_mux_e;
 
typedef enum pin_open_drain {
    PIN_OPEN_DRAIN  = 0U,   
    PIN_PUSH_PULL   = 2U,   
} pin_open_drain_e;
 
typedef enum pin_pull_config {
    PIN_NOPULL     = 0U,    
    PIN_PULL_DOWN  = 1U,    
    PIN_PULL_UP    = 2U,    
} pin_pull_config_e;
 
typedef enum pin_drive_strength {
    PIN_DS_2MA  = 0U,       
    PIN_DS_8MA  = 1U,       
    PIN_DS_4MA  = 2U,       
    PIN_DS_12MA = 3U,       
} pin_drive_strength_e;
 
typedef enum pin_slew_rate {
    PIN_SR_FAST  = 0U,      
    PIN_SR_SLOW  = 1U,      
} pin_slew_rate_e;
 
typedef enum pin_input_select {
    PIN_IS_CMOS          = 0U,  
    PIN_IS_CMOS_SCHMITT  = 1U,  
} pin_input_select_e;
 
typedef enum pin_data_direction {
    PIN_INPUT_DIRECTION  = 0U,  
    PIN_OUTPUT_DIRECTION = 1U,  
} pin_data_direction_e;
 
typedef enum pin_interrupt_config {
    PIN_INTERRUPT_DISABLED     = 0U,    
    PIN_INTERRUPT_HIGH_LEVEL   = 1U,    
    PIN_INTERRUPT_LOW_LEVEL    = 2U,    
    PIN_INTERRUPT_RISING_EDGE  = 3U,    
    PIN_INTERRUPT_FALLING_EDGE = 4U,    
    PIN_INTERRUPT_BOTH_EDGE    = 5U,    
} pin_interrupt_config_e;
 
typedef enum pin_level_type {
    PIN_LEVEL_LOW  = 0U,    
    PIN_LEVEL_HIGH = 1U,    
} pin_level_type_e;
 
typedef enum pin_force_input {
    PIN_FORCE_INPUT_NORMAL  = 0U,   
    PIN_FORCE_INPUT_ENABLE  = 1U,   
    PIN_FORCE_INPUT_HIGH    = 2U,   
    PIN_FORCE_INPUT_LOW     = 3U,   
} pin_force_input_e;
 
typedef enum pin_mode_select {
    PIN_MODE_DIGITAL            = 0U,   
    PIN_MODE_SELECT_NORMAL      = 1U,   
    PIN_MODE_DOWN_CONVERSION    = 2U    
} pin_mode_select_e;
 
typedef struct pin_settings_config {
    uint32_t                  pin_index;        
    pin_mux_e                 mux;              
    pin_open_drain_e          open_drain;       
    pin_pull_config_e         pull_config;      
    pin_drive_strength_e      drive_strength;   
    pin_slew_rate_e           slew_rate;        
    pin_input_select_e        input_select;     
    pin_data_direction_e      data_direction;   
    pin_interrupt_config_e    interrupt_config; 
    pin_level_type_e          initial_value;    
    pin_force_input_e         force_input;      
    pin_mode_select_e         mode_select;      
} pin_settings_config_t;
 
 
status_t sdrv_pinctrl_init(uint32_t count, const pin_settings_config_t *configs);
 
status_t sdrv_pinctrl_set_mux(uint32_t pin_index, pin_mux_e mux);
 
status_t sdrv_pinctrl_set_opendrain(uint32_t pin_index, pin_open_drain_e open_drain);
 
status_t sdrv_pinctrl_set_pull(uint32_t pin_index, pin_pull_config_e pull_config);
 
status_t sdrv_pinctrl_set_drive_strength(uint32_t pin_index, pin_drive_strength_e drive_strength);
 
status_t sdrv_pinctrl_set_slew_rate(uint32_t pin_index, pin_slew_rate_e slew_rate);
 
status_t sdrv_pinctrl_set_input_select(uint32_t pin_index, pin_input_select_e input_select);
 
status_t sdrv_pinctrl_set_force_input(uint32_t pin_index, pin_force_input_e force_input);
 
status_t sdrv_pinctrl_set_mode_select(uint32_t pin_index, pin_mode_select_e mode_select);
 
status_t sdrv_pinctrl_clear_dispmux_config(void);
 
status_t sdrv_pinctrl_set_high_resistance(uint32_t pin_index);
 
status_t sdrv_pinctrl_ctrl_init_pin(sdrv_pinctrl_t *pinctrl, struct sdrv_gpio *gpio, const pin_settings_config_t *pin_cfg);
 
status_t sdrv_pinctrl_ctrl_set_mux(sdrv_pinctrl_t *pinctrl, uint32_t pin_index, pin_mux_e mux);
 
status_t sdrv_pinctrl_ctrl_set_opendrain(sdrv_pinctrl_t *pinctrl, uint32_t pin_index, pin_open_drain_e open_drain);
 
status_t sdrv_pinctrl_ctrl_set_pull(sdrv_pinctrl_t *pinctrl, uint32_t pin_index, pin_pull_config_e pull_config);
 
status_t sdrv_pinctrl_ctrl_set_drive_strength(sdrv_pinctrl_t *pinctrl, uint32_t pin_index, pin_drive_strength_e drive_strength);
 
status_t sdrv_pinctrl_ctrl_set_slew_rate(sdrv_pinctrl_t *pinctrl, uint32_t pin_index, pin_slew_rate_e slew_rate);
 
status_t sdrv_pinctrl_ctrl_set_input_select(sdrv_pinctrl_t *pinctrl, uint32_t pin_index, pin_input_select_e input_select);
 
status_t sdrv_pinctrl_ctrl_set_force_input(sdrv_pinctrl_t *pinctrl, uint32_t pin_index, pin_force_input_e force_input);
 
status_t sdrv_pinctrl_ctrl_set_mode_select(sdrv_pinctrl_t *pinctrl, uint32_t pin_index, pin_mode_select_e mode_select);
 
status_t sdrv_pinctrl_ctrl_clear_dispmux_config(sdrv_pinctrl_t *pinctrl);
 
status_t sdrv_pinctrl_ctrl_set_high_resistance(sdrv_pinctrl_t *pinctrl, struct sdrv_gpio *gpio, uint32_t pin_index);
 
#endif /* SDRV_PINCTRL_H_ */