gama_regs.h

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#ifndef __GAMA_REGS_H__
#define __GAMA_REGS_H__
 
#define GAMA_LB_JUMP 0x00200000
#define GAMA_IB_JUMP 0x00100000
#define GAMA_IRQST_JUMP 0x000F0000
#define GAMA_ASW_JUMP 0x00030000
#define GAMA_DMA_JUMP 0x00020000
#define GAMA_FRS_JUMP 0x00011000
#define GAMA_VS_JUMP 0x00010000
#define GAMA_STN_CFG_JUMP 0x00000000
 
#define ASW_REG(x) ((x) + GAMA_ASW_JUMP)
 
/* GAMA ASW registers (RMW mode) definition */
 
/* ASW_FCTRL */
#define ASW_FCTRL ASW_REG(0x0)
#define ASW_M2M_FS_SHIFT 0
#define ASW_M2M_FS_MASK 0x1 << ASW_M2M_FS_SHIFT
 
/*ASW_SOFT_RESET*/
#define ASW_SOFT_RESET ASW_REG(0x4)
#define ASW_SOFT_RESET_SHIFT 0
#define ASW_SOFT_RESET_MASK 0x1 << ASW_SOFT_RESET_SHIFT
 
/*ASW_PARA_SET*/
#define ASW_PARA_SET ASW_REG(0x8)
#define CSI_LN_START_ASW_SHIFT 20
#define CSI_LN_START_ASW_MASK 0xFFFUL << CSI_LN_START_ASW_SHIFT
#define ASW_DC_BUF_SIZE_SHIFT 12
#define ASW_DC_BUF_SIZE_MASK 0x3 << ASW_DC_BUF_SIZE_SHIFT
#define EXT_LUT_FORMAT_SHIFT 11
#define EXT_LUT_FORMAT_MASK 0x1 << EXT_LUT_FORMAT_SHIFT
#define EXT_CSPLINE_EN_SHIFT 10
#define EXT_CSPLINE_EN_MASK 0x1 << EXT_CSPLINE_EN_SHIFT
#define WORK_MODE_SHIFT 8
#define WORK_MODE_MASK 0x3 << WORK_MODE_SHIFT
#define CACHE_N_WAY_SHIFT 4
#define CACHE_N_WAY_MASK 0xF << CACHE_N_WAY_SHIFT
#define C_ENTRY_TYPE_SHIFT 1
#define C_ENTRY_TYPE_MASK 0x7 << C_ENTRY_TYPE_SHIFT
#define LUT_INTERP_MODE_SHIFT 0
#define LUT_INTERP_MODE_MASK 0x1 << LUT_INTERP_MODE_SHIFT
 
/*ASW_PARA_SET1*/
#define ASW_PARA_SET1 ASW_REG(0xc)
#define UV_V_OFFSET_SHIFT 12
#define UV_V_OFFSET_MASK 0x3 << UV_V_OFFSET_SHIFT
#define UV_H_OFFSET_SHIFT 10
#define UV_H_OFFSET_MASK 0x3 << UV_H_OFFSET_SHIFT
#define ADB_OFFSET_SHIFT 4
#define ADB_OFFSET_MASK 0x3F << ADB_OFFSET_SHIFT
#define ADB_SLOPE_SHIFT 0
#define ADB_SLOPE_MASK 0xF << ADB_SLOPE_SHIFT
 
/*ASW_SRC_RES*/
#define ASW_SRC_RES ASW_REG(0x10)
#define SRC_RES_VSIZE_SHIFT 16
#define SRC_RES_VSIZE_MASK 0xFFF << SRC_RES_VSIZE_SHIFT
#define SRC_RES_HSIZE_SHIFT 0
#define SRC_RES_HSIZE_MASK 0xFFF << SRC_RES_HSIZE_SHIFT
 
/*ASW_DES_RES*/
#define ASW_DES_RES ASW_REG(0x14)
#define DES_RES_VSIZE_SHIFT 16
#define DES_RES_VSIZE_MASK 0xFFF << DES_RES_VSIZE_SHIFT
#define DES_RES_HSIZE_SHIFT 0
#define DES_RES_HSIZE_MASK 0xFFF << DES_RES_HSIZE_SHIFT
 
/*ASW_IMG_FMT*/
#define ASW_IMG_FMT ASW_REG(0x18)
#define DES_VFLIP_SHIFT 25
#define DES_VFLIP_MASK 0x1 << DES_VFLIP_SHIFT
#define DES_HFLIP_SHIFT 24
#define DES_HFLIP_MASK 0x1 << DES_HFLIP_SHIFT
#define DES_FMT_SHIFT 16
#define DES_FMT_MASK 0xF << DES_FMT_SHIFT
#define SRC_VFLIP_SHIFT 9
#define SRC_VFLIP_MASK 0x1 << SRC_VFLIP_SHIFT
#define SRC_HFLIP_SHIFT 8
#define SRC_HFLIP_MASK 0x1 << SRC_HFLIP_SHIFT
#define SRC_FMT_SHIFT 0
#define SRC_FMT_MASK 0xF << SRC_FMT_SHIFT
 
/*ASW_CFG_PROT*/
#define ASW_CFG_PORT ASW_REG(0x1c)
#define ADR_PORT_BIT_SHIFT 1
#define ADR_PORT_BIT_MASK 0x1 << ADR_PORT_BIT_SHIFT
#define CFG_PORT_BIT_SHIFT 0
#define CFG_PORT_BIT_MASK 0x1 << CFG_PORT_BIT_SHIFT
 
/*ASW_LUT_SIZE*/
#define ASW_LUT_SIZE ASW_REG(0x20)
#define LUT_SIZE_HEIGHT_SHIFT 16
#define LUT_SIZE_HEIGHT_MASK 0x3FF << LUT_SIZE_HEIGHT_SHIFT
#define LUT_SIZE_WIDTH_SHIFT 0
#define LUT_SIZE_WIDTH_MASK 0x3FF << LUT_SIZE_WIDTH_SHIFT
 
/*ASW_LUT_STEP*/
#define ASW_LUT_STEP ASW_REG(0x24)
#define LUT_STEP_VVAL_SHIFT 16
#define LUT_STEP_VVAL_MASK 0xFFF << LUT_STEP_VVAL_SHIFT
#define LUT_STEP_HVAL_SHIFT 0
#define LUT_STEP_HVAL_MASK 0xFFF << LUT_STEP_HVAL_SHIFT
 
/*ASW_LUT_SETPH_RECP*/
#define ASW_LUT_SETPH_RECP ASW_REG(0x28)
#define LUT_SETPH_RECP_VAL_SHIFT 0
#define LUT_SETPH_RECP_VAL_MASK 0xFFFFF << LUT_SETPH_RECP_VAL_SHIFT
 
/*ASW_LUT_SETPV_RECP*/
#define ASW_LUT_SETPV_RECP ASW_REG(0x2c)
#define LUT_SETPV_RECP_VAL_SHIFT 0
#define LUT_SETPV_RECP_VAL_MASK 0xFFFFF << LUT_SETPV_RECP_VAL_SHIFT
 
/*ASW_POS_CALC_PFILE_BA*/
#define ASW_POS_CALC_PFILE_BA ASW_REG(0x30)
 
/*ASW_POS_LUT_BA*/
#define ASW_POS_LUT_BA ASW_REG(0x34)
 
/*ASW_POS_M_V_BA*/
#define ASW_POS_M_V_BA ASW_REG(0x38)
 
/*ASW_RY_CACHE_BA*/
#define ASW_RY_CACHE_BA ASW_REG(0x40)
 
/*ASW_GU_CACHE_BA*/
#define ASW_GU_CACHE_BA ASW_REG(0x44)
 
/*ASW_BV_CACHE_BA*/
#define ASW_BV_CACHE_BA ASW_REG(0x48)
 
/*ASW_A_CACHE_BA*/
#define ASW_A_CACHE_BA ASW_REG(0x4c)
 
/*ASW_PIX_R_BA*/
#define ASW_PIX_R_BA ASW_REG(0x50)
 
/*ASW_PIX_R_STRIDE*/
#define ASW_PIX_R_STRIDE ASW_REG(0x58)
 
/*ASW_SRC_RY_BA*/
#define ASW_SRC_RY_BA ASW_REG(0x60)
 
/*ASW_SRC_GU_BA*/
#define ASW_SRC_GU_BA ASW_REG(0x64)
 
/*ASW_SRC_BV_BA*/
#define ASW_SRC_BV_BA ASW_REG(0x68)
 
/*ASW_SRC_RY_STRIDE*/
#define ASW_SRC_RY_STRIDE ASW_REG(0x6c)
 
/*ASW_SRC_GU_STRIDE*/
#define ASW_SRC_GU_STRIDE ASW_REG(0x70)
 
/*ASW_SRC_BV_STRIDE*/
#define ASW_SRC_BV_STRIDE ASW_REG(0x74)
 
/*ASW_DES_BA*/
#define ASW_DES_BA ASW_REG(0x80)
 
/*ASW_DES_STRIDE*/
#define ASW_DES_STRIDE ASW_REG(0x84)
 
/*ASW_DES_BG_COLOR*/
#define ASW_DES_BG_COLOR ASW_REG(0x88)
#define DES_BG_COLOR_A_VAL_SHIFT 24
#define DES_BG_COLOR_A_VAL_MASK 0xFF << DES_BG_COLOR_A_VAL_SHIFT
#define DES_BG_COLOR_B_VAL_SHIFT 16
#define DES_BG_COLOR_B_VAL_MASK 0xFF << DES_BG_COLOR_B_VAL_SHIFT
#define DES_BG_COLOR_G_VAL_SHIFT 8
#define DES_BG_COLOR_G_VAL_MASK 0xFF << DES_BG_COLOR_G_VAL_SHIFT
#define DES_BG_COLOR_R_VAL_SHIFT 0
#define DES_BG_COLOR_R_VAL_MASK 0xFF << DES_BG_COLOR_R_VAL_SHIFT
 
/*ASW_EXT_MLUT_RX_BA*/
#define ASW_EXT_MLUT_RX_BA ASW_REG(0x90)
 
/*ASW_EXT_MLUT_RY_BA*/
#define ASW_EXT_MLUT_RY_BA ASW_REG(0x94)
 
/*ASW_EXT_MLUT_GX_BA*/
#define ASW_EXT_MLUT_GX_BA ASW_REG(0x98)
 
/*ASW_EXT_MLUT_GY_BA*/
#define ASW_EXT_MLUT_GY_BA ASW_REG(0x9c)
 
/*ASW_EXT_MLUT_BX_BA*/
#define ASW_EXT_MLUT_BX_BA ASW_REG(0xa0)
 
/*ASW_EXT_MLUT_BY_BA*/
#define ASW_EXT_MLUT_BY_BA ASW_REG(0xa4)
 
/*ASW_EXT_MLUT_RX_STRIDE*/
#define ASW_EXT_MLUT_RX_STRIDE ASW_REG(0xa8)
 
/*ASW_EXT_MLUT_RY_STRIDE*/
#define ASW_EXT_MLUT_RY_STRIDE ASW_REG(0xac)
 
/*ASW_EXT_MLUT_GX_STRIDE*/
#define ASW_EXT_MLUT_GX_STRIDE ASW_REG(0xb0)
 
/*ASW_EXT_MLUT_GY_STRIDE*/
#define ASW_EXT_MLUT_GY_STRIDE ASW_REG(0xb4)
 
/*ASW_EXT_MLUT_BX_STRIDE*/
#define ASW_EXT_MLUT_BX_STRIDE ASW_REG(0xb8)
 
/*ASW_EXT_MLUT_RY_STRIDE*/
#define ASW_EXT_MLUT_BY_STRIDE ASW_REG(0xbc)
 
/*ASW_ABNORM_HANDLE*/
#define ASW_ABNORM_HANDLE ASW_REG(0xe0)
#define LB_LUT_TYPE_SHIFT 2
#define LB_LUT_TYPE_MASK 0x3 << LB_LUT_TYPE_SHIFT
#define RECOVERY_MODE_SHIFT 1
#define RECOVERY_MODE_MASK 00x1 << RECOVERY_MODE_SHIFT
#define LN_UPDATE_EN_SHIFT 0
#define LN_UPDATE_EN_MASK 0x1 << LN_UPDATE_EN_SHIFT
 
/*ASW_JP_LB_PROG*/
#define ASW_JP_LB_PROG ASW_REG(0xe4)
 
/*ASW_CLOAD_PEAK_BW*/
#define ASW_CLOAD_PEAK_BW ASW_REG(0xf0)
 
/*ASW_CLOAD_TOTAL_BW*/
#define ASW_CLOAD_TOTAL_BW ASW_REG(0xf4)
 
/*ASW_POS_ST*/
#define ASW_POS_ST ASW_REG(0xf8)
 
/*ASW_FR_OUT_ST*/
#define ASW_FR_OUT_ST ASW_REG(0xfc)
 
/*ASW_DBG_POS_ST0*/
#define ASW_DBG_POS_ST0 ASW_REG(0x100)
 
/*ASW_DBG_POS_ST1*/
#define ASW_DBG_POS_ST1 ASW_REG(0x104)
 
/*ASW_DBG_POS_ST2*/
#define ASW_DBG_POS_ST2 ASW_REG(0x108)
 
/*ASW_DBG_POS_ST3*/
#define ASW_DBG_POS_ST3 ASW_REG(0x10c)
 
/*ASW_DBG_POS_ST4*/
#define ASW_DBG_POS_ST4 ASW_REG(0x110)
 
/*ASW_DBG_POS_ST5*/
#define ASW_DBG_POS_ST5 ASW_REG(0x114)
 
/*ASW_DBG_DBC_ST0*/
#define ASW_DBG_DBC_ST0 ASW_REG(0x118)
 
/*ASW_DBG_DBC_ST1*/
#define ASW_DBG_DBC_ST1 ASW_REG(0x11c)
 
/*ASW_DBG_DBC_ST2*/
#define ASW_DBG_DBC_ST2 ASW_REG(0x120)
 
/*ASW_DBG_DBC_ST3*/
#define ASW_DBG_DBC_ST3 ASW_REG(0x124)
 
/*ASW_DBG_LBC_ST0*/
#define ASW_DBG_LBC_ST0 ASW_REG(0x128)
 
/*ASW_DBG_LBC_ST1*/
#define ASW_DBG_LBC_ST1 ASW_REG(0x12c)
 
/****irqst ab0*****/
 
#define IRQST_REG(x) ((x) + GAMA_IRQST_JUMP)
 
/*GAMA_HW_MODE*/
#define GAMA_HW_MODE IRQST_REG(0x10)
#define DMA_WR_LB_TO_SHIFT 26
#define DMA_WR_LB_TO_MASK 0x3F << DMA_WR_LB_TO_SHIFT
#define DMA_RD_LB_TO_SHIFT 20
#define DMA_RD_LB_TO_MASK 0x3F << DMA_RD_LB_TO_SHIFT
#define AHB_RW_LB_TO_SHIFT 14
#define AHB_RW_LB_TO_MASK 0x3F << AHB_RW_LB_TO_SHIFT
#define LB_REQ_PRIORITY_SHIFT 12
#define LB_REQ_PRIORITY_MASK 0x3 << LB_REQ_PRIORITY_SHIFT
#define DMA_WR_LB_TO_EN_SHIFT 11
#define DMA_WR_LB_TO_EN_MASK 0x1 << DMA_WR_LB_TO_EN_SHIFT
#define DMA_RD_LB_TO_EN_SHIFT 10
#define DMA_RD_LB_TO_EN_MASK 0x1 << DMA_RD_LB_TO_EN_SHIFT
#define AHB_RW_LB_TO_EN_SHIFT 9
#define AHB_RW_LB_TO_EN_MASK 0x1 << AHB_RW_LB_TO_EN_SHIFT
#define ASW_EN_SHIFT 2
#define ASW_EN_MASK 0x1 << ASW_EN_SHIFT
#define LB_LAYOUT_TYPE_SHIFT 1
#define LB_LAYOUT_TYPE_MASK 0x1 << LB_LAYOUT_TYPE_SHIFT
#define EPU_CTRL_MODE_SHIFT 0
#define EPU_CTRL_MODE_MASK 0x1 << EPU_CTRL_MODE_SHIFT
 
/*irqst ab0*/
 
#define INT_ST1 IRQST_REG(0x1024)
#define INT_MSK1 IRQST_REG(0x1028)
#define INT_PTY1 IRQST_REG(0x102c)
#define INT_CLR1 IRQST_REG(0x1030)
#define INT_SET1 IRQST_REG(0x1034)
 
#define WRITE_OUT_FRM_DONE_SHIFT 0
#define WRITE_OUT_FRM_DONE_MASK 1 << WRITE_OUT_FRM_DONE_SHIFT
 
/*dma*/
 
#define DMA_REG(x) ((x) + GAMA_DMA_JUMP)
#define RD_CHN_NUM 3
#define RD_CHN_JUMP 0x40
#define WD_CHN_NUM 2
#define WD_CHN_JUMP 0x40
 
#define RDMA_SRC_CFG_(i) (DMA_REG(0x0) + RD_CHN_JUMP * (i))
#define WDMA_DST_CFG_(i) (DMA_REG(0xc) + WD_CHN_JUMP * (i))
#define RDMA_PRIORITY_SHIFT 30
#define RDMA_PRIORITY_MASK 0x3 << RDMA_PRIORITY_SHIFT
#define RDMA_BURST_LEN_SHIFT 20
#define RDMA_BURST_LEN_MASK 0xF << RDMA_BURST_LEN_SHIFT
#define RDMA_STRIDE_SHIFT 0
#define RDMA_STRIDE_MASK 0xFFFFF << RDMA_STRIDE_SHIFT
 
#define RDMA_CFIFO_DEPTH_(i) (DMA_REG(0x10) + RD_CHN_JUMP * (i))
#define RDMA_DFIFO_DEPTH_(i) (DMA_REG(0x14) + RD_CHN_JUMP * (i))
 
#define RDMA_AXI_CTRL_(i) (DMA_REG(0x18) + RD_CHN_JUMP * (i))
#define RDMA_AXI_PROT_SHIFT 4
#define RDMA_AXI_PROT_MASK 0x3 << RDMA_AXI_PROT_SHIFT
#define RDMA_AXI_CACHE_SHIFT 0
#define RDMA_AXI_CACHE_MASK 0xF << RDMA_AXI_CACHE_SHIFT
 
#define RDMA_ADDR_LOW_(i) (DMA_REG(0x1c) + RD_CHN_JUMP * (i))
#define RDMA_ADDR_HIGH_(i) (DMA_REG(0x20) + RD_CHN_JUMP * (i))
 
#define RDMA_FB_CTRL_(i) (DMA_REG(0x24) + RD_CHN_JUMP * (i))
#define RDMA_FB_WRAP_RAGNGE_SHIFT 1
#define RDMA_FB_WRAP_RAGNGE_MASK 0x7 << RDMA_FB_WRAP_RAGNGE_SHIFT
#define RDMA_FB_CIRCULAR_EN_SHIFT 0
#define RDMA_FB_CIRCULAR_EN_MASK 0x1 << RDMA_FB_CIRCULAR_EN_SHIFT
 
#define RDMA_CTRL DMA_REG(0x1000)
#define RDMA_CFG_LOAD_SHIFT 1
#define RDMA_CFG_LOAD_MASK 0x1 << RDMA_CFG_LOAD_SHIFT
#define RDMA_ARB_SEL_SHIFT 0
#define RDMA_ARB_SEL_MASK 0x1 << RDMA_ARB_SEL_SHIFT
 
#define WDMA_CFIFO_DEPTH_(i) (DMA_REG(0x2000) + WD_CHN_JUMP * (i))
#define WDMA_DFIFO_DEPTH_(i) (DMA_REG(0x2004) + WD_CHN_JUMP * (i))
 
#define WDMA_AXI_CTRL_(i) (DMA_REG(0x2008) + WD_CHN_JUMP * (i))
#define WDMA_AXI_CHN_RST_SHIFT 7
#define WDMA_AXI_CHN_RST_MASK 0x1 << WDMA_AXI_CHN_RST_SHIFT
#define WDMA_AXI_BUFAB_CFG_SHIFT 6
#define WDMA_AXI_BUFAB_CFG_MASK 0x7F << WDMA_AXI_BUFAB_CFG_SHIFT
#define WDMA_AXI_PROT_SHIFT 4
#define WDMA_AXI_PROT_MASK 0x3 << WDMA_AXI_PROT_SHIFT
#define WDMA_AXI_CACHE_SHIFT 0
#define WDMA_AXI_CACHE_MASK 0xF << WDMA_AXI_CACHE_SHIFT
 
#define WDMA_ADDR_LOW_(i) (DMA_REG(0x200c) + WD_CHN_JUMP * (i))
#define WDMA_ADDR_HIGH_(i) (DMA_REG(0x2010) + WD_CHN_JUMP * (i))
 
#define WDMA_FB_CTRL_(i) (DMA_REG(0x2014) + WD_CHN_JUMP * (i))
#define WDMA_FB_WRAP_RAGNGE_SHIFT 1
#define WDMA_FB_WRAP_RAGNGE_MASK 0x7 << WDMA_FB_WRAP_RAGNGE_SHIFT
#define WDMA_FB_CIRCULAR_EN_SHIFT 0
#define WDMA_FB_CIRCULAR_EN_MASK 0x1 << WDMA_FB_CIRCULAR_EN_SHIFT
 
#define WDMA_CTRL DMA_REG(0x3000)
#define WDMA_CFG_LOAD_SHIFT 1
#define WDMA_CFG_LOAD_MASK 0x1 << WDMA_CFG_LOAD_SHIFT
#define WDMA_ARB_SEL_SHIFT 0
#define WDMA_ARB_SEL_MASK 0x1 << WDMA_ARB_SEL_SHIFT
 
#endif //__GAMA_REGS_H__