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liumin
2026-04-18 09:16:58 +08:00
parent 2b49081589
commit 1575212f13
10236 changed files with 72 additions and 1436438 deletions
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411
drivers/include/asw/asw.h Normal file
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/**
* @file asw.h
* @brief SemiDrive asw header file.
*
* @copyright Copyright (c) 2022 Semidrive Semiconductor.
* All rights reserved.
*/
#ifndef __ASW_H__
#define __ASW_H__
#include <types.h>
#if CONFIG_OS_FREERTOS
#include <FreeRTOS.h>
#include <semphr.h>
#endif
#include "asw_g_use.h"
#include "asw_lut_hvk.h"
/*fmt*/
/*DES FMT support: */
/* FMT_MONOTONIC_8BIT */
/* FMT_RGB565 */
/* FMT_RGBA5551 */
/* FMT_ARGB1555 */
/* FMT_RGB_YUV888 */
/* FMT_YUV422_UYVY */
/* FMT_YUV422_VYUY */
/* FMT_RGBA8888 */
/* FMT_ARGB8888 */
/* FMT_YUV422_YUYV */
/* FMT_YUV422_YVYU */
/*SRC FMT support: */
/* FMT_MONOTONIC_8BIT */
/* FMT_RGB_YUV888_PLANAR*/
/* FMT_YUV422_PLANAR */
/* FMT_YUV420_PLANAR */
/* FMT_RGB565 */
/* FMT_RGBA5551 */
/* FMT_ARGB1555 */
/* FMT_RGB_YUV888 */
/* FMT_YUV422_SEMI_U0V0 */
/* FMT_YUV422_SEMI_V0U0 */
/* FMT_RGBA8888 */
/* FMT_ARGB8888 */
enum {
FMT_MONOTONIC_8BIT = 0,
FMT_RGB_YUV888_PLANAR = 1,
FMT_YUV422_PLANAR = 2,
FMT_YUV420_PLANAR = 3,
FMT_RGB565 = 4,
FMT_RGBA5551 = 5,
FMT_ARGB1555 = 6,
FMT_RGB_YUV888 = 8,
FMT_YUV422_SEMI_U0V0 = 9,
FMT_YUV422_SEMI_V0U0 = 10,
FMT_RGBA8888 = 12,
FMT_ARGB8888 = 13,
FMT_YUV422_YUYV = 14,
FMT_YUV422_YVYU = 15
};
#define FMT_YUV422_UYVY 9
#define FMT_YUV422_VYUY 10
enum { LB_LAYOUT_A = 0, LB_LAYOUT_B };
enum { LUT_MODE_BILINEAR = 0, LUT_MODE_CUBIC_SPLINE };
enum { EXT_LUT_FORMAT_16BIT = 0, EXT_LUT_FORMAT_32BIT };
enum { CUBIC_MODE_INT_ASM = 0, CUBIC_MODE_EXT_ASM };
/*cache entry type (hsize x vsize)*/
enum {
C_ENTRY_TYPE_8X4 = 0,
C_ENTRY_TYPE_8X8,
C_ENTRY_TYPE_16X4,
C_ENTRY_TYPE_16X8,
C_ENTRY_TYPE_32X4
};
enum {
BUF_SIZE_8LINES = 0,
BUF_SIZE_16LINES,
BUF_SIZE_32LINES,
BUF_SIZE_64LINES
};
enum {
FLIP_TYPE_NONE = 0,
FLIP_TYPE_HFLIP = 1,
FLIP_TYPE_VFLIP = 2,
FLIP_TYPE_HVFLIP = 3
};
enum TRIAG_YTPE {
TRIAG_LEFT_TOP = 0,
TRIAG_LEFT_BOTTOM,
TRIAG_TYPE_RIGHT_TOP,
TRIAG_TYPE_RIGHT_BOTTOM
};
struct asw_config {
paddr_t base;
int irq;
};
/**@brief This structure include ASW output image configuration information*/
struct dst_info {
int dst_fmt; /**< Output image format*/
int dst_hsize; /**< Output image width (unit: pixel)*/
int dst_vsize; /**< Output image height (unit:line)*/
int dst_ba; /**< Output image memory base address*/
int dst_stride; /**< Output image pitch*/
int dst_bg_color; /**< Output image background color*/
int dst_flip; /**< Output image flip mode select*/
};
/**@brief This structure include ASW input image information*/
struct src_info {
int src_fmt; /**< Input image format*/
int src_hsize; /**< Input image width (unit: pixel)*/
int src_vsize; /**< Input image height (unit: line)*/
int src_ry_ba; /**< Input image first plane memory base address*/
int src_gu_ba; /**< Input image second plane memory base address*/
int src_bv_ba; /**< Input image third plane memory base address*/
int src_ry_stride; /**< Input image first plane pitch*/
int src_gu_stride; /**< Input image second plane pitch*/
int src_bv_stride; /**< Input image third plane pitch*/
int src_flip; /**< Input image flip mode select*/
};
/**@brief This structure include lookup table size and step information*/
struct lut_info {
int asw_lut_hsize; /**< Lookup table horizontal size*/
int asw_lut_vsize; /**< Lookup table vertical size*/
int asw_lut_hstep; /**< Lookup table horizontal step size*/
int asw_lut_vstep; /**< Lookup table vertical step size*/
};
struct cubic_info {
int lut_src_ba;
int alpha_src_ba;
};
/**@brief This structure include bilinear spline lookup table information*/
struct ext_info {
int ext_mlut_rx_ba; /**< First plane x position lookup table external memory
base address*/
int ext_mlut_ry_ba; /**< First plane y position lookup table external memory
base address*/
int ext_mlut_gx_ba; /**< Second plane x position lookup table external
memory base address*/
int ext_mlut_gy_ba; /**< Second plane y position lookup table external
memory base address*/
int ext_mlut_bx_ba; /**< Third plane x position lookup table external memory
base address*/
int ext_mlut_by_ba; /**< Third plane y position lookup table external
memory base address*/
int ext_mlut_rx_stride; /**< First plane x position lookup table external
memory pitch*/
int ext_mlut_ry_stride; /**< First plane y position lookup table external
memory pitch*/
int ext_mlut_gx_stride; /**< Second plane x position lookup table external
memory pitch*/
int ext_mlut_gy_stride; /**< Second plane y position lookup table external
memory pitch*/
int ext_mlut_bx_stride; /**< Third plane x position lookup table external
memory pitch*/
int ext_mlut_by_stride; /**< Third plane y position lookup table external
memory pitch*/
};
/**@brief adb info struct*/
struct adb_info {
int dirty; /**< 0:using system default offset&&slop;1:using this
offset&&slop*/
int offset; /**< range[0-0x3f]*/
int slope; /**< range[0-0xf]*/
};
struct circular_buf {
int enable;
int range;
int low_limit_addr;
int high_limit_addr;
};
/**@brief This structure includes all the configuration information of ASW for
* controlling the ASW’s work*/
struct asw_input {
int work_mode; /**< ASW work mode select*/
int hdsk_mode; /**< ASW output buffer size (only "Display coupled mode" and
"CSI and display tightly coupled ultra low latency mode"
using)*/
int lut_mode; /**< LUT mode select*/
int ext_lut_fmt; /**< Bilinear external LUT format select*/
struct dst_info dst; /**< ASW output image information*/
struct src_info src; /**< ASW input image information*/
struct lut_info lut; /**< LUT information*/
struct adb_info adb; /**< adb information*/
int cache_entry_type; /**< cache entry type select (hsize x vsize)*/
int cache_way_n; /**< cache way number (unit: cache entry vsize)*/
struct cubic_info
cubic; /**< spline LUT, alpha source (only cubic spline using)*/
struct ext_info ext; /**< bilinear spline external LUT base address*/
int csi_start_ln; /**< When using "CSI coupled mode" or "CSI and display
tightly coupled ultra low latency mode", this line is
written out from CSI to RAM to start ASW*/
struct circular_buf cbuf;
};
struct asw_ba_info {
int asw_pos_calc_pfile_ba;
int asw_pos_lut_ba;
int asw_m_v_ba;
int asw_alpha_ba;
int asw_y_stepy_ba;
int asw_lut_h_ba;
int asw_m_h_ba;
int asw_frb_ba;
int asw_cache_ry_ba;
int asw_cache_gu_ba;
int asw_cache_bv_ba;
int asw_cache_a_ba;
};
/**@brief This structure include rotation informations*/
struct asw_rot {
int hsize; /**< Image width (unit: pixel)*/
int vsize; /**< Image height (unit: line)*/
double angle; /**< Rotation angle*/
int dst_fmt; /**< Output image format*/
int dst_ba; /**< Output image memory base address*/
int dst_stride; /**< Output image pitch*/
int src_fmt; /**< Input image format*/
int src_ba[4]; /**< Input image memory base address*/
int src_stride[4]; /**< Input image pitch*/
int t_buf;
int t_stride;
int bg_color; /**< Output image background color*/
};
/**@brief This struct include asw draw triangle input infomations*/
struct asw_ratria {
int type; /**< triangle type, value in enum TRIAG_TYPE*/
int fmt; /**< buffer format, only support FMT_RGB565, FMT_RGBA5551,
FMT_ARGB1555, FMT_RGB_YUV888, FMT_RGBA8888, FMT_ARGB8888*/
int color; /**< B:bit[31:24], G:bit[23:16], R:bit[15:8], A:bit[7:0]*/
int hsize;
int vsize;
int pos_x; /**< the position x in buffer*/
int pos_y; /**< the position y in buffer*/
int addr; /**< buffer base address*/
int stride; /**< buffer pitch*/
};
struct asw_operations;
/**@brief This structure describe the ASW information and function opeartaions*/
struct asw_dev {
paddr_t base; /**< ASW register base address*/
int irq; /**< ASW irq number*/
struct asw_ba_info bas; /**< Parts base address in ASW local buffer*/
struct asw_operations *ops; /**< ASW function operations*/
struct asw_input *input; /**< Configure information of ASW*/
struct asw_app_asw app; /**< Application information*/
int asw_done; /**< flags for asw done*/
#if CONFIG_OS_FREERTOS
SemaphoreHandle_t wdone_sema; /** < sema for asw done>*/
#endif
};
struct asw_operations {
void (*soft_reset)(struct asw_dev *dev);
void (*cubic_cfg)(struct asw_dev *dev);
void (*cubic_cfg_with_hvkt)(struct asw_dev *dev, struct hvkt_param *hvkt);
void (*cubic_rotation)(struct asw_dev *dev, double rotate_angle,
struct hvkt_param *hvkt);
void (*bilinear_cfg)(struct asw_dev *dev);
void (*bilinear_cfg_with_hvkt)(struct asw_dev *dev,
struct hvkt_param *hvkt);
void (*bilinear_rotation)(struct asw_dev *dev, double rotate_angle,
struct hvkt_param *hvkt);
int (*irq_handler)(unsigned int irq, void *arg);
};
extern struct asw_dev aswdev;
extern int is_asw_done;
void sdrv_asw_probe(struct asw_dev *dev, const struct asw_config *asw_cfg);
/**
* @brief sdrv asw cubic.
*
* This function performs warp task with cubic spline lookup table.
*
* @param [in] input All the configuration information of ASW for controlling
* the ASW’s work.
*/
void sdrv_asw_cubic(struct asw_input *input);
/**
* @brief sdrv asw cubic with hvkt.
*
* This function performs warp task with cubic spline h/v keystone infomation.
*
* @param [in] input All the configuration information of ASW for controlling
* the ASW’s work.
* @param [in] hvkt h/v keystone information.
*
*/
void sdrv_asw_cubic_with_hvkt(struct asw_input *input, struct hvkt_param *hvkt);
/**
* @brief sdrv asw bilinear.
*
* This function performs warp task with bilinear spline lookup tables.
* @param [in] input All the configuration information of ASW for controlling.
*/
void sdrv_asw_bilinear(struct asw_input *input);
/**
* @brief sdrv asw bilinear noblock.
*
* This function performs warp task with bilinear spline lookup tables.
*
* @param [in] input All the configuration information of ASW for controlling.
**/
void sdrv_asw_bilinear_noblock(struct asw_input *input);
/**
* @brief sdrv asw bilinear with hvkt.
*
* This function performs warp task with bilinear spline h/v keystone
* infomation.
*
* @param [in] input All the configuration information of ASW for controlling
* the ASW’s work.
* @param [in] hvkt: h/v keystone information.
*/
void sdrv_asw_bilinear_with_hvkt(struct asw_input *input,
struct hvkt_param *hvkt);
/**
* @brief sdrv asw bilinear ftob32.
*
* Covert data from float type to int type.
*
* @param [in] faddr source data array point with float data type.
* @param [in] b32 dst data array point with int data type.
* @param [in] len convert data length.
*/
void sdrv_asw_bilinear_ftob32(const float *faddr, int *b32, int len);
/**
* @brief sdrv asw bilinear ftob16.
*
* Covert data from float type to short type.
*
* @param [in] faddr source data array point with float data type.
* @param [in] b16 dst data array point with short data type.
* @param [in] len convert data length.
*/
void sdrv_asw_bilinear_ftob16(const float *faddr, short *b16, int len);
/**
* @brief sdrv asw bilinear rotation.
*
* Image rotation with bilinear algorithm.
*
* @param [in] rot rotation infomation.
*/
void sdrv_asw_bilinear_rotation(struct asw_rot *rot);
/**
* @brief sdrv asw ra triangle.
*
* This function can draw right-angled triangle.
*
* @param [in] info right-angled triangle infomation.
*/
void sdrv_asw_ra_triangle(struct asw_ratria *info);
/**
* @brief sdrv asw fill rect.
*
* This function can fill rectangle with single color.
*
* @param [in] fmt buffer format.
* @param [in] color B:bit[31:24], G:bit[23:16], R:bit[15:8], A:bit[7:0].
* @param [in] hsize the active size of width.
* @param [in] vsize the active size of height.
* @param [in] pos_x the position of x in buffer.
* @param [in] pos_y the position of y in buffer.
* @param [in] addr buffer base address.
* @param [in] stride buffer pitch.
*/
void sdrv_asw_fill_rect(int fmt, int color, int hsize, int vsize, int pos_x,
int pos_y, int addr, int stride);
#endif //__GAMA_H__

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drivers/include/asw/asw_g_use.h Normal file
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/**
* @file asw_g_use.h
* @brief SemiDrive asw header file.
*
* @copyright Copyright (c) 2022 Semidrive Semiconductor.
* All rights reserved.
*/
#ifndef __ASW_G_USE_H__
#define __ASW_G_USE_H__
/*application id*/
enum ASW_APP_ID {
ASW_APP_NONE = 0,
ASW_APP_EMIRROR,
};
enum {
WORK_MODE_M_TO_M = 0,
WORK_MODE_CSI_HS,
WORK_MODE_DC_HS,
WORK_MODE_CSI_DC_HS
};
struct asw_app_dc {
int id;
int work_mode; /**< M_TO_M, CSI_HS, DC_HS, CSI_DC_HS*/
int mode; /**< 0:bilinear, 1: cubic spline*/
int buf_size_num_lines;
int t_delta;
int out_buf[2];
int buf_index;
};
struct asw_app_asw {
int id;
int work_mode;
int out_buf[2]; /**< only for csi-asw handshake*/
int out_index;
int ext_lut_x[2];
int ext_lut_y[2];
int swap;
};
#endif

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drivers/include/asw/asw_log.h Normal file
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/**
* @file asw_log.h
* @brief SemiDrive asw log header file.
*
* @copyright Copyright (c) 2022 Semidrive Semiconductor.
* All rights reserved.
*/
#ifndef ASW_LOG_H__
#define ASW_LOG_H__
#include <debug.h>
#define ASW_LOG_ENABLE 1
#define ASW_LOG_LEVEL_EMERG SSDK_EMERG /*System is unusable*/
#define ASW_LOG_LEVEL_ALERT SSDK_ALERT /*Action must be taken immediately*/
#define ASW_LOG_LEVEL_CRIT SSDK_CRIT /*Critical conditions*/
#define ASW_LOG_LEVEL_ERR SSDK_ERR /*Error conditions*/
#define ASW_LOG_LEVEL_WARN SSDK_WARNING /*Warning conditions*/
#define ASW_LOG_LEVEL_NOTICE \
SSDK_NOTICE /*Normal, but significant, \
conditions*/
#define ASW_LOG_LEVEL_INFO SSDK_INFO /*Informational message*/
#define ASW_LOG_LEVEL_DEBUG SSDK_DEBUG /*Debug-level message*/
/*log level default*/
#define ASW_LOG_LEVEL ASW_LOG_LEVEL_ERR
#define ASW_LOG_EMERG(string, args...) \
if (ASW_LOG_ENABLE && (ASW_LOG_LEVEL >= ASW_LOG_LEVEL_EMERG)) { \
ssdk_printf(ASW_LOG_LEVEL_EMERG, "[ASW]EMERG|%s| " string "\r\n", \
__func__, ##args); \
}
#define ASW_LOG_ALERT(string, args...) \
if (ASW_LOG_ENABLE && (ASW_LOG_LEVEL >= ASW_LOG_LEVEL_ALERT)) { \
ssdk_printf(ASW_LOG_LEVEL_ALERT, "[ASW]ALERT|%s| " string "\r\n", \
__func__, ##args); \
}
#define ASW_LOG_CRIT(string, args...) \
if (ASW_LOG_ENABLE && (ASW_LOG_LEVEL >= ASW_LOG_LEVEL_CRIT)) { \
ssdk_printf(ASW_LOG_LEVEL_CRIT, "[ASW]CRIT|%s| " string "\r\n", \
__func__, ##args); \
}
#define ASW_LOG_ERR(string, args...) \
if (ASW_LOG_ENABLE && (ASW_LOG_LEVEL >= ASW_LOG_LEVEL_ERR)) { \
ssdk_printf(ASW_LOG_LEVEL_ERR, "[ASW]ERR|%s| " string "\r\n", \
__func__, ##args); \
}
#define ASW_LOG_WARN(string, args...) \
if (ASW_LOG_ENABLE && (ASW_LOG_LEVEL >= ASW_LOG_LEVEL_WARN)) { \
ssdk_printf(ASW_LOG_LEVEL_WARN, "[ASW]WARN|%s| " string "\r\n", \
__func__, ##args); \
}
#define ASW_LOG_NOTICE(string, args...) \
if (ASW_LOG_ENABLE && (ASW_LOG_LEVEL >= ASW_LOG_LEVEL_NOTICE)) { \
ssdk_printf(ASW_LOG_LEVEL_NOTICE, "[ASW]NOTICE|%s| " string "\r\n", \
__func__, ##args); \
}
#define ASW_LOG_INFO(string, args...) \
if (ASW_LOG_ENABLE && (ASW_LOG_LEVEL >= ASW_LOG_LEVEL_INFO)) { \
ssdk_printf(ASW_LOG_LEVEL_INFO, "[ASW]INFO|%s| " string "\r\n", \
__func__, ##args); \
}
#define ASW_LOG_DEBUG(string, args...) \
if (ASW_LOG_ENABLE && (ASW_LOG_LEVEL >= ASW_LOG_LEVEL_DEBUG)) { \
ssdk_printf(ASW_LOG_LEVEL_DEBUG, "[ASW]DEBUG|%s| " string "\r\n", \
__func__, ##args); \
}
#define ASW_LOG_FUNC() \
if (ASW_LOG_ENABLE && (ASW_LOG_LEVEL >= ASW_LOG_LEVEL_INFO)) { \
ssdk_printf(ASW_LOG_LEVEL_INFO, "[ASW]FUNC|%s\r\n", __func__); \
}
#endif //_ASW_DRV_LOG_H__

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drivers/include/asw/asw_lut_hvk.h Normal file
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/**
* @file asw_lut_hvk.h
* @brief SemiDrive asw header file.
*
* @copyright Copyright (c) 2022 Semidrive Semiconductor.
* All rights reserved.
*/
#ifndef __HVTK_H__
#define __HVTK_H__
#include <math.h>
#include <types.h>
struct hvkt_fabc {
float fa0[3];
float fa1[3];
float fa2[3];
float fb0[3];
float fb1[3];
float fb2[3];
float fc0[3];
float fc1[3];
float fc2[3];
};
struct hvkt_param {
int chn;
bool fw_map;
float top_left_x[3];
float top_left_y[3];
float top_right_x[3];
float top_right_y[3];
float bottom_left_x[3];
float bottom_left_y[3];
float bottom_right_x[3];
float bottom_right_y[3];
int hsize; /**< the hsize of out size*/
int vsize; /**< the vsize of out size*/
int hsize_in; /**< the hszie of input size*/
int vsize_in; /**< the vsize of input size*/
int lut_h_size;
int lut_v_size;
int lut_h_step;
int lut_v_step;
int extend; /**< lut start extend*/
int lut_addr;
int m_v_addr;
int alpha_addr;
int ext_lut_addr;
struct hvkt_fabc *fabc;
bool is_external_lut;
int external_lut_format; /**< only for bilinear: 0: 16bit(1bit sign + 11bit
integer + 4bit fraction, 1: 32bit(13bit sign +
11bit integer + 8bit fraction))*/
int lut_real_addr[6]; /**< rx,ry,gx,gy,bx,by*/
int flip_type; /**< rotation*/
};
struct sdrv_lut_hvk_ops {
int (*lut_table_gen)(struct hvkt_param *hvkt);
int (*lut_m_v_gen)(struct hvkt_param *hvkt);
int (*lut_rotate_table_gen)(double angle, struct hvkt_param *hvkt);
};
extern struct sdrv_lut_hvk_ops lut_hvk_ops;
#endif //__HVTK_H__

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drivers/include/asw/gama_regs.h Normal file
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/**
* @file gama_regs.h
* @brief SemiDrive asw regs header file.
*
* @copyright Copyright (c) 2022 Semidrive Semiconductor.
* All rights reserved.
*/
#ifndef __GAMA_REGS_H__
#define __GAMA_REGS_H__
#define GAMA_LB_JUMP 0x00200000
#define GAMA_IB_JUMP 0x00100000
#define GAMA_IRQST_JUMP 0x000F0000
#define GAMA_ASW_JUMP 0x00030000
#define GAMA_DMA_JUMP 0x00020000
#define GAMA_FRS_JUMP 0x00011000
#define GAMA_VS_JUMP 0x00010000
#define GAMA_STN_CFG_JUMP 0x00000000
#define ASW_REG(x) ((x) + GAMA_ASW_JUMP)
/* GAMA ASW registers (RMW mode) definition */
/* ASW_RA000 */
#define ASW_RA000 ASW_REG(0x0)
#define ASW_SHIFT00_RA000 0
#define ASW_MASK00_RA000 0x1 << ASW_SHIFT00_RA000
/*ASW_RA004*/
#define ASW_RA004 ASW_REG(0x4)
#define ASW_SHIFT00_RA004 0
#define ASW_MASK00_RA004 0x1 << ASW_SHIFT00_RA004
/*ASW_RA008*/
#define ASW_RA008 ASW_REG(0x8)
#define ASW_SHIFT20_RA008 20
#define ASW_MASK20_RA008 0xFFFUL << ASW_SHIFT20_RA008
#define ASW_SHIFT12_RA008 12
#define ASW_MASK12_RA008 0x3 << ASW_SHIFT12_RA008
#define ASW_SHIFT11_RA008 11
#define ASW_MASK11_RA008 0x1 << ASW_SHIFT11_RA008
#define ASW_SHIFT10_RA008 10
#define ASW_MASK10_RA008 0x1 << ASW_SHIFT10_RA008
#define ASW_SHIFT08_RA008 8
#define ASW_MASK08_RA008 0x3 << ASW_SHIFT08_RA008
#define ASW_SHIFT04_RA008 4
#define ASW_MASK04_RA008 0xF << ASW_SHIFT04_RA008
#define ASW_SHIFT01_RA008 1
#define ASW_MASK01_RA008 0x7 << ASW_SHIFT01_RA008
#define ASW_SHIFT00_RA008 0
#define ASW_MASK00_RA008 0x1 << ASW_SHIFT00_RA008
/*ASW_RA00C*/
#define ASW_RA00C ASW_REG(0xc)
#define ASW_SHIFT12_RA00C 12
#define ASW_MASK12_RA00C 0x3 << ASW_SHIFT12_RA00C
#define ASW_SHIFT10_RA00C 10
#define ASW_MASK10_RA00C 0x3 << ASW_SHIFT10_RA00C
#define ASW_SHIFT04_RA00C 4
#define ASW_MASK04_RA00C 0x3F << ASW_SHIFT04_RA00C
#define ASW_SHIFT00_RA00C 0
#define ASW_MASK00_RA00C 0xF << ASW_SHIFT00_RA00C
/*ASW_RA010*/
#define ASW_RA010 ASW_REG(0x10)
#define ASW_SHIFT16_RA010 16
#define ASW_MASK16_RA010 0xFFF << ASW_SHIFT16_RA010
#define ASW_SHIFT00_RA010 0
#define ASW_MASK00_RA010 0xFFF << ASW_SHIFT00_RA010
/*ASW_RA014*/
#define ASW_RA014 ASW_REG(0x14)
#define ASW_SHIFT16_RA014 16
#define ASW_MASK16_RA014 0xFFF << ASW_SHIFT16_RA014
#define ASW_SHIFT00_RA014 0
#define ASW_MASK00_RA014 0xFFF << ASW_SHIFT00_RA014
/*ASW_RA018*/
#define ASW_RA018 ASW_REG(0x18)
#define ASW_SHIFT25_RA018 25
#define ASW_MASK25_RA018 0x1 << ASW_SHIFT25_RA018
#define ASW_SHIFT24_RA018 24
#define ASW_MASK24_RA018 0x1 << ASW_SHIFT24_RA018
#define ASW_SHIFT16_RA018 16
#define ASW_MASK16_RA018 0xF << ASW_SHIFT16_RA018
#define ASW_SHIFT09_RA018 9
#define ASW_MASK09_RA018 0x1 << ASW_SHIFT09_RA018
#define ASW_SHIFT08_RA018 8
#define ASW_MASK08_RA018 0x1 << ASW_SHIFT08_RA018
#define ASW_SHIFT00_RA018 0
#define ASW_MASK00_RA018 0xF << ASW_SHIFT00_RA018
/*ASW_CFG_PROT*/
#define ASW_RA01C ASW_REG(0x1c)
#define ASW_SHIFT01_RA01C 1
#define ASW_MASK01_RA01C 0x1 << ASW_SHIFT01_RA01C
#define ASW_SHIFT00_RA01C 0
#define ASW_MASK00_RA01C 0x1 << ASW_SHIFT00_RA01C
/*ASW_RA020*/
#define ASW_RA020 ASW_REG(0x20)
#define ASW_SHIFT16_RA020 16
#define ASW_MASK16_RA020 0x3FF << ASW_SHIFT16_RA020
#define ASW_SHIFT00_RA020 0
#define ASW_MASK00_RA020 0x3FF << ASW_SHIFT00_RA020
/*ASW_RA024*/
#define ASW_RA024 ASW_REG(0x24)
#define ASW_SHIFT16_RA024 16
#define ASW_MASK16_RA024 0xFFF << ASW_SHIFT16_RA024
#define ASW_SHIFT00_RA024 0
#define ASW_MASK00_RA024 0xFFF << ASW_SHIFT00_RA024
/*ASW_RA028*/
#define ASW_RA028 ASW_REG(0x28)
#define ASW_SHIFT00_RA028 0
#define ASW_MASK00_RA028 0xFFFFF << ASW_SHIFT00_RA028
/*ASW_RA02C*/
#define ASW_RA02C ASW_REG(0x2c)
#define LUT_SETPV_RECP_VAL_SHIFT 0
#define LUT_SETPV_RECP_VAL_MASK 0xFFFFF << LUT_SETPV_RECP_VAL_SHIFT
/*ASW_RA030*/
#define ASW_RA030 ASW_REG(0x30)
/*ASW_RA034*/
#define ASW_RA034 ASW_REG(0x34)
/*ASW_RA038*/
#define ASW_RA038 ASW_REG(0x38)
/*ASW_RA040*/
#define ASW_RA040 ASW_REG(0x40)
/*ASW_RA044*/
#define ASW_RA044 ASW_REG(0x44)
/*ASW_RA048*/
#define ASW_RA048 ASW_REG(0x48)
/*ASW_RA04C*/
#define ASW_RA04C ASW_REG(0x4c)
/*ASW_RA050*/
#define ASW_RA050 ASW_REG(0x50)
/*ASW_RA058*/
#define ASW_RA058 ASW_REG(0x58)
/*ASW_RA060*/
#define ASW_RA060 ASW_REG(0x60)
/*ASW_RA064*/
#define ASW_RA064 ASW_REG(0x64)
/*ASW_RA068*/
#define ASW_RA068 ASW_REG(0x68)
/*ASW_RA06C*/
#define ASW_RA06C ASW_REG(0x6c)
/*ASW_RA070*/
#define ASW_RA070 ASW_REG(0x70)
/*ASW_RA074*/
#define ASW_RA074 ASW_REG(0x74)
/*ASW_RA080*/
#define ASW_RA080 ASW_REG(0x80)
/*ASW_RA084*/
#define ASW_RA084 ASW_REG(0x84)
/*ASW_RA088*/
#define ASW_RA088 ASW_REG(0x88)
#define ASW_SHIFT24_RA088 24
#define ASW_MASK24_RA088 0xFF << ASW_SHIFT24_RA088
#define ASW_SHIFT16_RA088 16
#define ASW_MASK16_RA088 0xFF << ASW_SHIFT16_RA088
#define ASW_SHIFT08_RA088 8
#define ASW_MASK08_RA088 0xFF << ASW_SHIFT08_RA088
#define ASW_SHIFT00_RA088 0
#define ASW_MASK00_RA088 0xFF << ASW_SHIFT00_RA088
/*ASW_RA090*/
#define ASW_RA090 ASW_REG(0x90)
/*ASW_RA094*/
#define ASW_RA094 ASW_REG(0x94)
/*ASW_RA098*/
#define ASW_RA098 ASW_REG(0x98)
/*ASW_RA09C*/
#define ASW_RA09C ASW_REG(0x9c)
/*ASW_RA0A0*/
#define ASW_RA0A0 ASW_REG(0xa0)
/*ASW_RA0A4*/
#define ASW_RA0A4 ASW_REG(0xa4)
/*ASW_RA0A8*/
#define ASW_RA0A8 ASW_REG(0xa8)
/*ASW_RA0AC*/
#define ASW_RA0AC ASW_REG(0xac)
/*ASW_RA0B0*/
#define ASW_RA0B0 ASW_REG(0xb0)
/*ASW_RA0B4*/
#define ASW_RA0B4 ASW_REG(0xb4)
/*ASW_RA0B8*/
#define ASW_RA0B8 ASW_REG(0xb8)
/*ASW_RA0AC*/
#define ASW_RA0BC ASW_REG(0xbc)
/*ASW_RA0E0*/
#define ASW_RA0E0 ASW_REG(0xe0)
#define ASW_SHIFT02_RA0E0 2
#define ASW_MASK02_RA0E0 0x3 << ASW_SHIFT02_RA0E0
#define ASW_SHIFT01_RA0E0 1
#define ASW_MASK01_RA0E0 00x1 << ASW_SHIFT01_RA0E0
#define ASW_SHIFT00_RA0E0 0
#define ASW_MASK00_RA0E0 0x1 << ASW_SHIFT00_RA0E0
/*ASW_RA0E4*/
#define ASW_RA0E4 ASW_REG(0xe4)
/*ASW_RA0F0*/
#define ASW_RA0F0 ASW_REG(0xf0)
/*ASW_RA0F4*/
#define ASW_RA0F4 ASW_REG(0xf4)
/*ASW_RA0F8*/
#define ASW_RA0F8 ASW_REG(0xf8)
/*ASW_RA0FC*/
#define ASW_RA0FC ASW_REG(0xfc)
/*ASW_RA100*/
#define ASW_RA100 ASW_REG(0x100)
/*ASW_RA104*/
#define ASW_RA104 ASW_REG(0x104)
/*ASW_RA108*/
#define ASW_RA108 ASW_REG(0x108)
/*ASW_RA10C*/
#define ASW_RA10C ASW_REG(0x10c)
/*ASW_RA110*/
#define ASW_RA110 ASW_REG(0x110)
/*ASW_RA114*/
#define ASW_RA114 ASW_REG(0x114)
/*ASW_RA118*/
#define ASW_RA118 ASW_REG(0x118)
/*ASW_RA11C*/
#define ASW_RA11C ASW_REG(0x11c)
/*ASW_RA120*/
#define ASW_RA120 ASW_REG(0x120)
/*ASW_RA124*/
#define ASW_RA124 ASW_REG(0x124)
/*ASW_RA128*/
#define ASW_RA128 ASW_REG(0x128)
/*ASW_RA12C*/
#define ASW_RA12C ASW_REG(0x12c)
/****irqst ab0*****/
#define IRQST_REG(x) ((x) + GAMA_IRQST_JUMP)
/*ASW_RB010*/
#define ASW_RB010 IRQST_REG(0x10)
#define ASW_SHIFT26_RB010 26
#define ASW_MASK26_RB010 0x3F << ASW_SHIFT26_RB010
#define ASW_SHIFT20_RB010 20
#define ASW_MASK20_RB010 0x3F << ASW_SHIFT20_RB010
#define ASW_SHIFT14_RB010 14
#define ASW_MASK14_RB010 0x3F << ASW_SHIFT14_RB010
#define ASW_SHIFT12_RB010 12
#define ASW_MASK12_RB010 0x3 << ASW_SHIFT12_RB010
#define ASW_SHIFT11_RB010 11
#define ASW_MASK11_RB010 0x1 << ASW_SHIFT11_RB010
#define ASW_SHIFT10_RB010 10
#define ASW_MASK10_RB010 0x1 << ASW_SHIFT10_RB010
#define ASW_SHIFT09_RB010 9
#define ASW_MASK09_RB010 0x1 << ASW_SHIFT09_RB010
#define ASW_SHIFT02_RB010 2
#define ASW_MASK02_RB010 0x1 << ASW_SHIFT02_RB010
#define ASW_SHIFT01_RB010 1
#define ASW_MASK01_RB010 0x1 << ASW_SHIFT01_RB010
#define ASW_SHIFT00_RB010 0
#define ASW_MASK00_RB010 0x1 << ASW_SHIFT00_RB010
/*irqst ab0*/
#define ASW_RC024 IRQST_REG(0x1024)
#define ASW_RC028 IRQST_REG(0x1028)
#define ASW_RC02C IRQST_REG(0x102c)
#define ASW_RC030 IRQST_REG(0x1030)
#define ASW_RC034 IRQST_REG(0x1034)
#define WRITE_OUT_FRM_DONE_SHIFT 0
#define WRITE_OUT_FRM_DONE_MASK 1 << WRITE_OUT_FRM_DONE_SHIFT
/*dma*/
#define DMA_REG(x) ((x) + GAMA_DMA_JUMP)
#define RD_CHN_NUM 3
#define RD_CHN_JUMP 0x40
#define WD_CHN_NUM 2
#define WD_CHN_JUMP 0x40
#define ASW_RD000(i) (DMA_REG(0x0) + RD_CHN_JUMP * (i))
#define ASW_RD00C(i) (DMA_REG(0xc) + WD_CHN_JUMP * (i))
#define ASW_SHIFT30_RD00X 30
#define ASW_MASK30_RD00X 0x3 << ASW_SHIFT30_RD00X
#define ASW_SHIFT20_RD00X 20
#define ASW_MASK20_RD00X 0xF << ASW_SHIFT20_RD00X
#define ASW_SHIFT00_RD00X 0
#define ASW_MASK00_RD00X 0xFFFFF << ASW_SHIFT00_RD00X
#define ASW_RD010(i) (DMA_REG(0x10) + RD_CHN_JUMP * (i))
#define ASW_RD014(i) (DMA_REG(0x14) + RD_CHN_JUMP * (i))
#define ASW_RD018(i) (DMA_REG(0x18) + RD_CHN_JUMP * (i))
#define ASW_SHIFT04_RD018 4
#define ASW_MASK04_RD018 0x3 << ASW_SHIFT04_RD018
#define ASW_SHIFT00_RD018 0
#define ASW_MASK00_RD018 0xF << ASW_SHIFT00_RD018
#define ASW_RD01C(i) (DMA_REG(0x1c) + RD_CHN_JUMP * (i))
#define ASW_RD020(i) (DMA_REG(0x20) + RD_CHN_JUMP * (i))
#define ASW_RD024(i) (DMA_REG(0x24) + RD_CHN_JUMP * (i))
#define ASW_SHIFT01_RD024 1
#define ASW_MASK01_RD024 0x7 << ASW_SHIFT01_RD024
#define ASW_SHIFT00_RD024 0
#define ASW_MASK00_RD024 0x1 << ASW_SHIFT00_RD024
#define ASW_RE000 DMA_REG(0x1000)
#define ASW_SHIFT01_RE000 1
#define ASW_MASK01_RE000 0x1 << ASW_SHIFT01_RE000
#define ASW_SHIFT00_RE000 0
#define ASW_MASK00_RE000 0x1 << ASW_SHIFT00_RE000
#define ASW_RF000(i) (DMA_REG(0x2000) + WD_CHN_JUMP * (i))
#define ASW_RF004(i) (DMA_REG(0x2004) + WD_CHN_JUMP * (i))
#define ASW_RF008(i) (DMA_REG(0x2008) + WD_CHN_JUMP * (i))
#define ASW_SHIFT07_RF008 7
#define ASW_MASK07_RF008 0x1 << ASW_SHIFT07_RF008
#define ASW_SHIFT06_RF008 6
#define ASW_MASK06_RF008 0x7F << ASW_SHIFT06_RF008
#define ASW_SHIFT04_RF008 4
#define ASW_MASK04_RF008 0x3 << ASW_SHIFT04_RF008
#define ASW_SHIFT00_RF008 0
#define ASW_MASK00_RF008 0xF << ASW_SHIFT00_RF008
#define ASW_RF00C(i) (DMA_REG(0x200c) + WD_CHN_JUMP * (i))
#define ASW_RF010(i) (DMA_REG(0x2010) + WD_CHN_JUMP * (i))
#define ASW_RF014(i) (DMA_REG(0x2014) + WD_CHN_JUMP * (i))
#define ASW_SHIFT01_RF014 1
#define ASW_MASK01_RF014 0x7 << ASW_SHIFT01_RF014
#define ASW_SHIFT00_RF014 0
#define ASW_MASK00_RF014 0x1 << ASW_SHIFT00_RF014
#define ASW_RG000 DMA_REG(0x3000)
#define ASW_SHIFT01_RG000 1
#define ASW_MASK01_RG000 0x1 << ASW_SHIFT01_RG000
#define ASW_SHIFT00_RG000 0
#define ASW_MASK00_RG000 0x1 << ASW_SHIFT00_RG000
#endif //__GAMA_REGS_H__