131 lines
3.5 KiB
C
131 lines
3.5 KiB
C
/**
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* @file rom_ctrl.c
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* @brief rom control source file
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*
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* @copyright Copyright (c) 2022 Semidrive Semiconductor.
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* All rights reserved.
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*/
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#include <armv7-r/barriers.h>
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#include <armv7-r/irq.h>
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#include <core_id.h>
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#include <part.h>
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#include <reg.h>
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#include <regs_base.h>
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#include <rom_ctrl/rom_ctrl.h>
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#include <reset_ip.h>
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#include <scr_hw.h>
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#include <sdrv_rstgen.h>
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#include <sdrv_scr.h>
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#define SFS_TAG 0x10000000
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#define SFS_READ_XFER_CONFIG0 0x10000040
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#define SFS_READ_XFER_CONFIG1 0x10000044
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#define SFS_TAG_VAL 0x53465301
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#define ROM_CTRL_FLASH_LINE_NUMBER_SHIFT 1
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#define ROM_CTRL_FLASH_CMD_SHIFT 3
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#define ROM_CTRL_FLASH_CTRL_VALID_SHIFT 5
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#define ROM_CTRL_BOOT_PIN_OVERRIDE_BIT_OFFSET 0x1
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#define ROM_CTRL_BOOT_PIN_OVERRIDE_ENABLE_BIT_OFFSET 0x9
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/**
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* @brief Read rom control data.
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*
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* @return rom control data
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*/
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static uint8_t get_rom_ctrl_data(void)
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{
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uint8_t line_num = 0;
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uint8_t ret = 0;
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#if CONFIG_RD_CFG_FROM_XSPI /* read config from xspi reg */
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uint32_t xspi_rd_cfg = readl(APB_XSPI1PORTA_BASE + 0x100);
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line_num = (xspi_rd_cfg >> 0) & 0x3;
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ret = (xspi_rd_cfg >> 26) & 0x1; // ddr or sdr
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#else /* read config from sfs file */
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if (readl(SFS_TAG) != SFS_TAG_VAL) {
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return 0;
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}
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else {
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line_num = (readl(SFS_READ_XFER_CONFIG0) >> 8) & 0x3;
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ret = (readl(SFS_READ_XFER_CONFIG1) >> 26) & 0x1; // ddr or sdr
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}
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#endif
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ret |= line_num << ROM_CTRL_FLASH_LINE_NUMBER_SHIFT; // line_num
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ret |= 0 << ROM_CTRL_FLASH_CMD_SHIFT; // cmd
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ret |= 1 << ROM_CTRL_FLASH_CTRL_VALID_SHIFT; // valid
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return ret;
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}
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/**
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* @brief Clear rom control boot pin mode flag.
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*
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* This function is used to clear rom control boot pin mode flag, call
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* this function and processor software reset, processor boot from
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* where is determined by the boot pin in hardware.
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*/
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static void sdrv_rom_ctrl_clear_boot_pin_flag(void)
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{
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uint32_t val = 0;
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val = sdrv_rstgen_read_general(&reset_general_reg_rom_ctrl);
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val &= ~0x1E;
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val &= ~(0x1 << ROM_CTRL_BOOT_PIN_OVERRIDE_ENABLE_BIT_OFFSET);
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sdrv_rstgen_write_general(&reset_general_reg_rom_ctrl, val);
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}
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/**
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* @brief Set rom control boot pin mode flag.
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*
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* This function is used to set rom control boot pin mode flag, call this
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* function and processor software reset, processor will boot from the
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* set mode.
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*
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* @param [in] boot_mode boot mode
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*/
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void sdrv_rom_ctrl_set_boot_pin_flag(sdrv_rom_ctrl_boot_mode_e boot_mode)
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{
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uint32_t val = 0;
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uint8_t boot_pin = 0;
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switch (boot_mode) {
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case SDRV_ROM_CTRL_BOOT_MODE_FLASH:
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boot_pin = 0;
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break;
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case SDRV_ROM_CTRL_BOOT_MODE_EMMC:
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boot_pin = 2;
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break;
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#if !CONFIG_E3L
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case SDRV_ROM_CTRL_BOOT_MODE_SD2:
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boot_pin = 4;
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break;
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#endif
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case SDRV_ROM_CTRL_BOOT_MODE_USB:
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boot_pin = 8;
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break;
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case SDRV_ROM_CTRL_BOOT_MODE_BOOT_PIN:
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default:
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sdrv_rom_ctrl_clear_boot_pin_flag();
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return;
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}
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val = sdrv_rstgen_read_general(&reset_general_reg_rom_ctrl);
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val |= ((boot_pin << ROM_CTRL_BOOT_PIN_OVERRIDE_BIT_OFFSET) & 0x1E);
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val |= (0x1 << ROM_CTRL_BOOT_PIN_OVERRIDE_ENABLE_BIT_OFFSET);
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sdrv_rstgen_write_general(&reset_general_reg_rom_ctrl, val);
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}
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/**
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* @brief Update rom control data.
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*/
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void sdrv_rom_ctrl_data_update(void)
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{
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/* update rom ctrl data */
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sdrv_rstgen_write_general_bit(&reset_general_reg_rom_ctrl, 24, 8, get_rom_ctrl_data());
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}
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