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2025-10-04 16:06:55 +08:00
commit 2acba0caf0
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interface_btm.c Normal file
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#include "regs_base.h"
#include "irq_num.h"
#include "sdrv_btm.h"
#include "interface_config.h"
//app<70><70><EFBFBD><EFBFBD>
#include "app/app_config.h"
static sdrv_btm_t gstsdrv_btm_timer0;
static sdrv_btm_t gstsdrv_btm_timer1;
volatile uint8_t Btm10ms = 0;
#define DEVICE_BASE(dev) _DEVICE_BASE(dev)
#define _DEVICE_BASE(dev) APB_##dev##_BASE
#define DEVICE_INTR(dev) _DEVICE_INTR(dev)
#define _DEVICE_INTR(dev) dev##_INTR_NUM
/*SDRV_BTM_G0ʱ<30><CAB1><EFBFBD><EFBFBD>Դ<EFBFBD><D4B4>APB clock, APB clock<63><6B><EFBFBD><EFBFBD>150MHz*/
/*SDRV_BTM_G0<47><30>Ƶ֮<C6B5><D6AE><EFBFBD><EFBFBD>clock<63><6B><EFBFBD><EFBFBD>1M*/
static sdrv_btm_cfg_t timer0_config = {
.base = DEVICE_BASE(BTM2),
.irq = DEVICE_INTR(BTM2_O_BTM),
.tmr_id = SDRV_BTM_G0,
.tmr_cfg = {
.si_val = 74, /*<2A><><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1>ÿ(si_val + 1)cycle, G0<47><30><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>inc_val<61><6C>*/
.inc_val = 1,
.frc_rld_rst_cnt_en = true, /*Ĭ<><C4AC><EFBFBD><EFBFBD>true<75><65><EFBFBD><EFBFBD>ʾ<EFBFBD><CABE>ʼ<EFBFBD><CABC>ʱ<EFBFBD>Ƿ<EFBFBD><C7B7><EFBFBD>counter<65><72><EFBFBD>㡣*/
.term_use_mode = SDRV_BTM_DIRECT, /*<2A><><EFBFBD><EFBFBD>overflowֵ<77><D6B5><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ч<EFBFBD><D0A7><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ǵȵ<C7B5><C8B5><EFBFBD>һ<EFBFBD><D2BB><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ч<EFBFBD><D0A7>*/
.cmp_use_mode = SDRV_BTM_DIRECT, /*<2A><><EFBFBD><EFBFBD>compareֵ<65><D6B5><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ч<EFBFBD><D0A7><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ǵȵ<C7B5><C8B5><EFBFBD>һ<EFBFBD><D2BB><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ч<EFBFBD><D0A7>*/
.cnt_dir = SDRV_BTM_CNT_UP, /*<2A><><EFBFBD>ü<EFBFBD><C3BC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ֵ<EFBFBD><D6B5><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>*/
.cnt_mode = SDRV_BTM_CONTINOUS_MODE, /*<2A><><EFBFBD>ü<EFBFBD><C3BC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ģʽ*/
}
};
/*SDRV_BTM_G1ʱ<31><CAB1><EFBFBD><EFBFBD>Դ<EFBFBD><D4B4><EFBFBD>ⲿ<EFBFBD><E2B2BF><EFBFBD>񣬵<EFBFBD><F1A3ACB5><EFBFBD>24MHz*/
/*SDRV_BTM_G1<47><31>Ƶ֮<C6B5><D6AE><EFBFBD><EFBFBD>clock<63><6B><EFBFBD><EFBFBD>1M*/
static sdrv_btm_cfg_t timer1_config = {
.base = DEVICE_BASE(BTM2),
.irq = DEVICE_INTR(BTM2_O_BTM),
.tmr_id = SDRV_BTM_G1,
.tmr_cfg = {
.si_val = 23,
.inc_val = 1,
.frc_rld_rst_cnt_en = true,
.term_use_mode = SDRV_BTM_DIRECT,
.cmp_use_mode = SDRV_BTM_DIRECT,
.cnt_dir = SDRV_BTM_CNT_UP,
.cnt_mode = SDRV_BTM_CONTINOUS_MODE,
}
};
//<2F>ص<EFBFBD><D8B5><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>10ms<6D><73>ʱ<EFBFBD><CAB1>־
static void timer1_handle(void *arg)
{
static int timer1_count = 0;
timer1_count++;
if(timer1_count >= 100)
{
timer1_count = 0;
Btm10ms = 1;
}
//app
timerUpdateAll(); // <20><><EFBFBD>ö<EFBFBD>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD><EFBFBD>º<EFBFBD><C2BA><EFBFBD>
}
/*<2A><><EFBFBD><EFBFBD>g1<67><31><EFBFBD><EFBFBD><EFBFBD><EFBFBD>*/
int btm_init(void)
{
sdrv_btm_init(&gstsdrv_btm_timer1, &timer0_config);//<2F><>ʱ<EFBFBD><CAB1>1<EFBFBD><31>ʼ<EFBFBD><CABC>
sdrv_btm_set_callback(&gstsdrv_btm_timer1, timer1_handle, &gstsdrv_btm_timer1);//<2F><EFBFBD>ص<EFBFBD><D8B5><EFBFBD><EFBFBD><EFBFBD>
sdrv_btm_start(&gstsdrv_btm_timer1, BTM_TYPE_PERIOD, BTM_TIME_US, 1000);//<2F>趨1000us<75><73>ʱ
sdrv_btm_init(&gstsdrv_btm_timer0, &timer1_config);//<2F><>ʱ<EFBFBD><CAB1>0<EFBFBD><30>ʼ<EFBFBD><CABC>
sdrv_btm_start(&gstsdrv_btm_timer0, BTM_TYPE_PERIOD, BTM_TIME_MS, ~0);//<2F>趨1ms<6D><73>ʱ
return 0;
}
//<2F><>ȡ<EFBFBD><C8A1>ǰ<EFBFBD><C7B0><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1>,lwip<69><70>
uint32_t current_time(void)
{
return sdrv_btm_get_current_time(&gstsdrv_btm_timer0) / 1000;
}
//<2F><>ȡ<EFBFBD><C8A1>ǰ<EFBFBD><C7B0><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1>us
uint32_t getCurrentTime(void)
{
return sdrv_btm_get_current_time(&gstsdrv_btm_timer0);
}