513 lines
18 KiB
C
513 lines
18 KiB
C
/**
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* @file saci_regs.h
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* @version 0.1
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* @date 2021-12-02
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*
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* @copyright Copyright (c) 2021 Semidrive Semiconductor.
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* All rights reserved.
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*
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*/
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#ifndef SDRV_SCAI_REGS_H_
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#define SDRV_SCAI_REGS_H_
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#include <types.h>
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#define SACI_0000_SACI_CTRL (0x0)
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#define SACI_0000_SACI_RST_POS (0x1f)
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#define SACI_0000_SACI_RST_MASK (0x80000000)
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#define SACI_0000_RX_ASYNC_RST_POS (0x11)
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#define SACI_0000_RX_ASYNC_RST_MASK (0x20000)
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#define SACI_0000_TX_ASYNC_RST_POS (0x10)
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#define SACI_0000_TX_ASYNC_RST_MASK (0x10000)
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#define SACI_0000_RX_A_FIFO_CLR_POS (0xc)
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#define SACI_0000_RX_A_FIFO_CLR_MASK (0x1000)
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#define SACI_0000_EXT_CLK_DIR_POS (0xb)
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#define SACI_0000_EXT_CLK_DIR_MASK (0x800)
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#define SACI_0000_EXT_CLK_SEL_POS (0xa)
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#define SACI_0000_EXT_CLK_SEL_MASK (0x400)
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#define SACI_0000_MCLK_DIR_POS (0x9)
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#define SACI_0000_MCLK_DIR_MASK (0x200)
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#define SACI_0000_MCLK_SEL_POS (0x8)
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#define SACI_0000_MCLK_SEL_MASK (0x100)
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#define SACI_0000_PDM_CH1_FIFO_FLUSH_POS (0x7)
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#define SACI_0000_PDM_CH1_FIFO_FLUSH_MASK (0x80)
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#define SACI_0000_PDM_CH0_FIFO_FLUSH_POS (0x6)
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#define SACI_0000_PDM_CH0_FIFO_FLUSH_MASK (0x40)
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#define SACI_0000_RX_FIFO_FLUSH_POS (0x5)
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#define SACI_0000_RX_FIFO_FLUSH_MASK (0x20)
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#define SACI_0000_TX_FIFO_FLUSH_POS (0x4)
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#define SACI_0000_TX_FIFO_FLUSH_MASK (0x10)
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#define SACI_0000_PDM_CH1_RST_POS (0x3)
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#define SACI_0000_PDM_CH1_RST_MASK (0x8)
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#define SACI_0000_PDM_CH0_RST_POS (0x2)
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#define SACI_0000_PDM_CH0_RST_MASK (0x4)
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#define SACI_0000_RX_RST_POS (0x1)
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#define SACI_0000_RX_RST_MASK (0x2)
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#define SACI_0000_TX_RST_POS (0x0)
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#define SACI_0000_TX_RST_MASK (0x1)
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#define SACI_0004_SACI_IRQ_MASK (0x4)
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#define SACI_0004_PDM_CH0_FIFO_PRE_FULL_POS (0x1f)
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#define SACI_0004_PDM_CH0_FIFO_PRE_FULL_MASK (0x80000000)
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#define SACI_0004_PDM_CH1_FIFO_PRE_FULL_POS (0x1e)
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#define SACI_0004_PDM_CH1_FIFO_PRE_FULL_MASK (0x40000000)
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#define SACI_0004_PDM_CH0_FIFO_EMPTY_POS (0x1d)
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#define SACI_0004_PDM_CH0_FIFO_EMPTY_MASK (0x20000000)
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#define SACI_0004_PDM_CH1_FIFO_EMPTY_POS (0x1c)
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#define SACI_0004_PDM_CH1_FIFO_EMPTY_MASK (0x10000000)
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#define SACI_0004_PDM_CH0_FIFO_FULL_POS (0x1b)
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#define SACI_0004_PDM_CH0_FIFO_FULL_MASK (0x8000000)
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#define SACI_0004_PDM_CH1_FIFO_FULL_POS (0x1a)
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#define SACI_0004_PDM_CH1_FIFO_FULL_MASK (0x4000000)
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#define SACI_0004_PDM_CH0_FIFO_OVR_POS (0x19)
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#define SACI_0004_PDM_CH0_FIFO_OVR_MASK (0x2000000)
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#define SACI_0004_PDM_CH1_FIFO_OVR_POS (0x18)
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#define SACI_0004_PDM_CH1_FIFO_OVR_MASK (0x1000000)
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#define SACI_0004_LPK_FAIL_CH5_POS (0x15)
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#define SACI_0004_LPK_FAIL_CH5_MASK (0x200000)
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#define SACI_0004_TX_FIFO_OVR_POS (0xe)
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#define SACI_0004_TX_FIFO_OVR_MASK (0x4000)
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#define SACI_0004_RX_FIFO_PRE_FULL_POS (0xd)
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#define SACI_0004_RX_FIFO_PRE_FULL_MASK (0x2000)
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#define SACI_0004_TX_FIFO_PRE_EMPTY_POS (0xc)
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#define SACI_0004_TX_FIFO_PRE_EMPTY_MASK (0x1000)
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#define SACI_0004_RX_TIMEOUT_POS (0xb)
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#define SACI_0004_RX_TIMEOUT_MASK (0x800)
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#define SACI_0004_RX_WIDTH_MISM_POS (0xa)
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#define SACI_0004_RX_WIDTH_MISM_MASK (0x400)
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#define SACI_0004_TX_WIDTH_MISM_POS (0x9)
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#define SACI_0004_TX_WIDTH_MISM_MASK (0x200)
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#define SACI_0004_PDM_CH0_WID_MISM_POS (0x8)
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#define SACI_0004_PDM_CH0_WID_MISM_MASK (0x100)
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#define SACI_0004_PDM_CH1_WID_MISM_POS (0x7)
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#define SACI_0004_PDM_CH1_WID_MISM_MASK (0x80)
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#define SACI_0004_RX_FIFO_EMPTY_POS (0x5)
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#define SACI_0004_RX_FIFO_EMPTY_MASK (0x20)
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#define SACI_0004_RX_FIFO_FULL_POS (0x4)
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#define SACI_0004_RX_FIFO_FULL_MASK (0x10)
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#define SACI_0004_RX_FIFO_OVR_POS (0x3)
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#define SACI_0004_RX_FIFO_OVR_MASK (0x8)
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#define SACI_0004_TX_FIFO_EMPTY_POS (0x2)
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#define SACI_0004_TX_FIFO_EMPTY_MASK (0x4)
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#define SACI_0004_TX_FIFO_FULL_POS (0x1)
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#define SACI_0004_TX_FIFO_FULL_MASK (0x2)
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#define SACI_0004_TX_FIFO_UDR_POS (0x0)
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#define SACI_0004_TX_FIFO_UDR_MASK (0x1)
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#define SACI_0008_SACI_IRQ_STAT (0x8)
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#define SACI_0008_PDM_CH0_FIFO_PRE_FULL_POS (0x1f)
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#define SACI_0008_PDM_CH0_FIFO_PRE_FULL_MASK (0x80000000)
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#define SACI_0008_PDM_CH1_FIFO_PRE_FULL_POS (0x1e)
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#define SACI_0008_PDM_CH1_FIFO_PRE_FULL_MASK (0x40000000)
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#define SACI_0008_PDM_CH0_FIFO_EMPTY_POS (0x1d)
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#define SACI_0008_PDM_CH0_FIFO_EMPTY_MASK (0x20000000)
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#define SACI_0008_PDM_CH1_FIFO_EMPTY_POS (0x1c)
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#define SACI_0008_PDM_CH1_FIFO_EMPTY_MASK (0x10000000)
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#define SACI_0008_PDM_CH0_FIFO_FULL_POS (0x1b)
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#define SACI_0008_PDM_CH0_FIFO_FULL_MASK (0x8000000)
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#define SACI_0008_PDM_CH1_FIFO_FULL_POS (0x1a)
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#define SACI_0008_PDM_CH1_FIFO_FULL_MASK (0x4000000)
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#define SACI_0008_PDM_CH0_FIFO_OVR_POS (0x19)
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#define SACI_0008_PDM_CH0_FIFO_OVR_MASK (0x2000000)
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#define SACI_0008_PDM_CH1_FIFO_OVR_POS (0x18)
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#define SACI_0008_PDM_CH1_FIFO_OVR_MASK (0x1000000)
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#define SACI_0008_LPK_FAIL_CH5_POS (0x15)
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#define SACI_0008_LPK_FAIL_CH5_MASK (0x200000)
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#define SACI_0008_TX_FIFO_OVR_POS (0xe)
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#define SACI_0008_TX_FIFO_OVR_MASK (0x4000)
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#define SACI_0008_RX_FIFO_PRE_FULL_POS (0xd)
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#define SACI_0008_RX_FIFO_PRE_FULL_MASK (0x2000)
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#define SACI_0008_TX_FIFO_PRE_EMPTY_POS (0xc)
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#define SACI_0008_TX_FIFO_PRE_EMPTY_MASK (0x1000)
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#define SACI_0008_RX_TIMEOUT_POS (0xb)
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#define SACI_0008_RX_TIMEOUT_MASK (0x800)
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#define SACI_0008_RX_WIDTH_MISM_POS (0xa)
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#define SACI_0008_RX_WIDTH_MISM_MASK (0x400)
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#define SACI_0008_TX_WIDTH_MISM_POS (0x9)
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#define SACI_0008_TX_WIDTH_MISM_MASK (0x200)
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#define SACI_0008_PDM_CH0_WID_MISM_POS (0x8)
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#define SACI_0008_PDM_CH0_WID_MISM_MASK (0x100)
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#define SACI_0008_PDM_CH1_WID_MISM_POS (0x7)
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#define SACI_0008_PDM_CH1_WID_MISM_MASK (0x80)
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#define SACI_0008_RX_FIFO_EMPTY_POS (0x5)
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#define SACI_0008_RX_FIFO_EMPTY_MASK (0x20)
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#define SACI_0008_RX_FIFO_FULL_POS (0x4)
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#define SACI_0008_RX_FIFO_FULL_MASK (0x10)
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#define SACI_0008_RX_FIFO_OVR_POS (0x3)
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#define SACI_0008_RX_FIFO_OVR_MASK (0x8)
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#define SACI_0008_TX_FIFO_EMPTY_POS (0x2)
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#define SACI_0008_TX_FIFO_EMPTY_MASK (0x4)
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#define SACI_0008_TX_FIFO_FULL_POS (0x1)
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#define SACI_0008_TX_FIFO_FULL_MASK (0x2)
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#define SACI_0008_TX_FIFO_UDR_POS (0x0)
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#define SACI_0008_TX_FIFO_UDR_MASK (0x1)
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#define SACI_000C_SACI_CH_CTRL (0xc)
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#define SACI_000C_CH7_DIR_POS (0x17)
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#define SACI_000C_CH7_DIR_MASK (0x800000)
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#define SACI_000C_CH6_DIR_POS (0x16)
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#define SACI_000C_CH6_DIR_MASK (0x400000)
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#define SACI_000C_CH5_DIR_POS (0x15)
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#define SACI_000C_CH5_DIR_MASK (0x200000)
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#define SACI_000C_CH4_DIR_POS (0x14)
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#define SACI_000C_CH4_DIR_MASK (0x100000)
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#define SACI_000C_CH3_DIR_POS (0x13)
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#define SACI_000C_CH3_DIR_MASK (0x80000)
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#define SACI_000C_CH2_DIR_POS (0x12)
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#define SACI_000C_CH2_DIR_MASK (0x40000)
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#define SACI_000C_CH1_DIR_POS (0x11)
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#define SACI_000C_CH1_DIR_MASK (0x20000)
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#define SACI_000C_CH0_DIR_POS (0x10)
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#define SACI_000C_CH0_DIR_MASK (0x10000)
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#define SACI_000C_CH7_EN_POS (0x7)
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#define SACI_000C_CH7_EN_MASK (0x80)
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#define SACI_000C_CH6_EN_POS (0x6)
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#define SACI_000C_CH6_EN_MASK (0x40)
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#define SACI_000C_CH5_EN_POS (0x5)
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#define SACI_000C_CH5_EN_MASK (0x20)
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#define SACI_000C_CH4_EN_POS (0x4)
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#define SACI_000C_CH4_EN_MASK (0x10)
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#define SACI_000C_CH3_EN_POS (0x3)
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#define SACI_000C_CH3_EN_MASK (0x8)
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#define SACI_000C_CH2_EN_POS (0x2)
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#define SACI_000C_CH2_EN_MASK (0x4)
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#define SACI_000C_CH1_EN_POS (0x1)
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#define SACI_000C_CH1_EN_MASK (0x2)
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#define SACI_000C_CH0_EN_POS (0x0)
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#define SACI_000C_CH0_EN_MASK (0x1)
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#define SACI_000C_CHx_DIR_POS (0x10)
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#define SACI_000C_CHx_DIR_MASK (0xFF0000)
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#define SACI_000C_CHx_EN_POS (0x0)
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#define SACI_000C_CHx_EN_MASK (0xFF)
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#define SACI_0010_SACI_LBK_CTRL (0x10)
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#define SACI_0010_CH_LPB_EN_POS (0x0)
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#define SACI_0010_CH_LPB_EN_MASK (0x3f)
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#define SACI_0010_RX_TIMEOUT_DMA_EN_POS (0x6)
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#define SACI_0010_RX_TIMEOUT_DMA_EN_MASK (0x40)
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#define SACI_1000_SACI_TX_CLK_CTRL (0x1000)
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#define SACI_1000_CLK_DIV_POS (0x10)
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#define SACI_1000_CLK_DIV_MASK (0xfff0000)
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#define SACI_1000_TSCK_LP_EN_POS (0x8)
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#define SACI_1000_TSCK_LP_EN_MASK (0x100)
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#define SACI_1000_SCK_OFFS_EN_POS (0x6)
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#define SACI_1000_SCK_OFFS_EN_MASK (0x40)
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#define SACI_1000_DIV_CLK_EN_POS (0x5)
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#define SACI_1000_DIV_CLK_EN_MASK (0x20)
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#define SACI_1000_CLK_O_EN_POS (0x4)
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#define SACI_1000_CLK_O_EN_MASK (0x10)
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#define SACI_1000_EXT_SYNC_EN_POS (0x3)
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#define SACI_1000_EXT_SYNC_EN_MASK (0x8)
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#define SACI_1000_CLK_SEL_POS (0x0)
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#define SACI_1000_CLK_SEL_MASK (0x7)
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#define SACI_1004_SACI_TX_CTRL (0x1004)
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#define SACI_1004_TX_DATA_SEL_POS (0x19)
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#define SACI_1004_TX_DATA_SEL_MASK (0x2000000)
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#define SACI_1004_DATA_ALIGN_POS (0x18)
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#define SACI_1004_DATA_ALIGN_MASK (0x1000000)
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#define SACI_1004_TX_MUTE_POS (0x17)
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#define SACI_1004_TX_MUTE_MASK (0x800000)
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#define SACI_1004_TX_DATA_WIDTH_POS (0x14)
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#define SACI_1004_TX_DATA_WIDTH_MASK (0x700000)
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#define SACI_1004_TX_CH_WIDTH_POS (0x11)
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#define SACI_1004_TX_CH_WIDTH_MASK (0xe0000)
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#define SACI_1004_TX_MONO_POS (0x10)
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#define SACI_1004_TX_MONO_MASK (0x10000)
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#define SACI_1004_TX_DMA_EN_POS (0xf)
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#define SACI_1004_TX_DMA_EN_MASK (0x8000)
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#define SACI_1004_TSCK_POL_POS (0xe)
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#define SACI_1004_TSCK_POL_MASK (0x4000)
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#define SACI_1004_TX_WS_OFFSET_POS (0xd)
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#define SACI_1004_TX_WS_OFFSET_MASK (0x2000)
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#define SACI_1004_TX_SYNC_MODE_POS (0xb)
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#define SACI_1004_TX_SYNC_MODE_MASK (0x1800)
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#define SACI_1004_TX_WS_LEN_POS (0x6)
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#define SACI_1004_TX_WS_LEN_MASK (0x7c0)
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#define SACI_1004_TX_WS_POL_POS (0x5)
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#define SACI_1004_TX_WS_POL_MASK (0x20)
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#define SACI_1004_TIMING_MODE_POS (0x2)
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#define SACI_1004_TIMING_MODE_MASK (0x1c)
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#define SACI_1004_TX_MODE_POS (0x1)
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#define SACI_1004_TX_MODE_MASK (0x2)
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#define SACI_1008_SACI_TX_FIFO_CTRL (0x1008)
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#define SACI_1008_THRD_POS (0x10)
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#define SACI_1008_THRD_MASK (0xfff0000)
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#define SACI_1008_TEST_EN_POS (0x8)
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#define SACI_1008_TEST_EN_MASK (0x100)
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#define SACI_1008_DATA_ALIGN_POS (0x1)
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#define SACI_1008_DATA_ALIGN_MASK (0x2)
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#define SACI_1008_DATA_PACK_MODE_POS (0x0)
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#define SACI_1008_DATA_PACK_MODE_MASK (0x1)
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#define SACI_100C_SACI_TX_FIFO_STA (0x100c)
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#define SACI_100C_FIFO_DPT_POS (0x10)
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#define SACI_100C_FIFO_DPT_MASK (0xfff0000)
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#define SACI_100C_FULL_POS (0x1)
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#define SACI_100C_FULL_MASK (0x2)
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#define SACI_100C_EMPTY_POS (0x0)
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#define SACI_100C_EMPTY_MASK (0x1)
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#define SACI_1010_SACI_TX_TDM_CTRL (0x1010)
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#define SACI_1010_CH_EN_POS (0x10)
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#define SACI_1010_CH_EN_MASK (0xffff0000)
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#define SACI_1010_CH_NUM_POS (0x4)
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#define SACI_1010_CH_NUM_MASK (0xf0)
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#define SACI_1010_OUT_SEL_POS (0x0)
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#define SACI_1010_OUT_SEL_MASK (0x7)
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#define SACI_1014_SACI_TX_EN (0x1014)
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#define SACI_1014_SLV_READY_POS (0x2)
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#define SACI_1014_SLV_READY_MASK (0x4)
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#define SACI_1014_EN_STAT_POS (0x1)
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#define SACI_1014_EN_STAT_MASK (0x02)
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#define SACI_1014_EN_POS (0x0)
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#define SACI_1014_EN_MASK (0x1)
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#define SACI_1018_SACI_TX_OFF_WAIT_TIME (0x1018)
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#define SACI_1018_CNT_POS (0x0)
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#define SACI_1018_CNT_MASK (0xffffffff)
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#define SACI_2000_SACI_TX_FIFO_DATA (0x2000)
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#define SACI_2000_SACI_TX_FIFO_DATA_POS (0x0)
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#define SACI_2000_SACI_TX_FIFO_DATA_MASK (0xffffffff)
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#define SACI_3000_SACI_RX_CLK_CTRL (0x3000)
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#define SACI_3000_CLK_DEV_POS (0x10)
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#define SACI_3000_CLK_DEV_MASK (0xfff0000)
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#define SACI_3000_RSCK_LP_EN_POS (0x8)
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#define SACI_3000_RSCK_LP_EN_MASK (0x100)
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#define SACI_3000_DIV_CLK_EN_POS (0x5)
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#define SACI_3000_DIV_CLK_EN_MASK (0x20)
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#define SACI_3000_CLK_O_EN_POS (0x4)
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#define SACI_3000_CLK_O_EN_MASK (0x10)
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#define SACI_3000_EXT_SYNC_EN_POS (0x3)
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#define SACI_3000_EXT_SYNC_EN_MASK (0x8)
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#define SACI_3000_CLK_SEL_POS (0x0)
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#define SACI_3000_CLK_SEL_MASK (0x7)
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#define SACI_3004_SACI_RX_CTRL (0x3004)
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#define SACI_3004_DATA_ALIGN_POS (0x18)
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#define SACI_3004_DATA_ALIGN_MASK (0x1000000)
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#define SACI_3004_RX_DATA_WIDTH_POS (0x14)
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#define SACI_3004_RX_DATA_WIDTH_MASK (0x700000)
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#define SACI_3004_RX_CH_WIDTH_POS (0x11)
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#define SACI_3004_RX_CH_WIDTH_MASK (0xe0000)
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#define SACI_3004_RX_MONO_POS (0x10)
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#define SACI_3004_RX_MONO_MASK (0x10000)
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#define SACI_3004_RX_DMA_EN_POS (0xf)
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#define SACI_3004_RX_DMA_EN_MASK (0x8000)
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#define SACI_3004_RSCK_POL_POS (0xe)
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#define SACI_3004_RSCK_POL_MASK (0x4000)
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#define SACI_3004_RX_WS_OFFSET_POS (0xd)
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#define SACI_3004_RX_WS_OFFSET_MASK (0x2000)
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#define SACI_3004_RX_SYNC_MODE_POS (0xb)
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#define SACI_3004_RX_SYNC_MODE_MASK (0x1800)
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#define SACI_3004_RX_WS_LEN_POS (0x6)
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#define SACI_3004_RX_WS_LEN_MASK (0x7c0)
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#define SACI_3004_RX_WS_POL_POS (0x5)
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#define SACI_3004_RX_WS_POL_MASK (0x20)
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#define SACI_3004_TIMING_MODE_POS (0x2)
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#define SACI_3004_TIMING_MODE_MASK (0x1c)
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#define SACI_3004_RX_MODE_POS (0x1)
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#define SACI_3004_RX_MODE_MASK (0x2)
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#define SACI_3008_SACI_RX_FIFO_CTRL (0x3008)
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#define SACI_3008_THRD_POS (0x10)
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#define SACI_3008_THRD_MASK (0xfff0000)
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#define SACI_3008_TEST_EN_POS (0x8)
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#define SACI_3008_TEST_EN_MASK (0x100)
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#define SACI_3008_DATA_ALIGN_POS (0x1)
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#define SACI_3008_DATA_ALIGN_MASK (0x2)
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#define SACI_3008_DATA_PACK_MODE_POS (0x0)
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#define SACI_3008_DATA_PACK_MODE_MASK (0x1)
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#define SACI_300C_SACI_RX_FIFO_STA (0x300c)
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#define SACI_300C_FIFO_DPT_POS (0x10)
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#define SACI_300C_FIFO_DPT_MASK (0xfff0000)
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#define SACI_300C_FULL_POS (0x1)
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#define SACI_300C_FULL_MASK (0x2)
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#define SACI_300C_EMPTY_POS (0x0)
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#define SACI_300C_EMPTY_MASK (0x1)
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#define SACI_3010_SACI_RX_TDM_CTRL (0x3010)
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#define SACI_3010_CH_EN_POS (0x10)
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#define SACI_3010_CH_EN_MASK (0xffff0000)
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#define SACI_3010_CH_NUM_POS (0x4)
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#define SACI_3010_CH_NUM_MASK (0xf0)
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#define SACI_3010_IN_SEL_POS (0x0)
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#define SACI_3010_IN_SEL_MASK (0x7)
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#define SACI_3014_SACI_RX_EN (0x3014)
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#define SACI_3014_SLV_READY_POS (0x2)
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#define SACI_3014_SLV_READY_MASK (0x4)
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#define SACI_3014_EN_STAT_POS (0x1)
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#define SACI_3014_EN_STAT_MASK (0x02)
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#define SACI_3014_EN_POS (0x0)
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#define SACI_3014_EN_MASK (0x1)
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#define SACI_3018_SACI_RX_TIMEOUT (0x3018)
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#define SACI_3018_THRD_POS (0x0)
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#define SACI_3018_THRD_MASK (0xffffffff)
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#define SACI_301C_SACI_RX_OFF_DELAY (0x301c)
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#define SACI_301C_THRD_POS (0x0)
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#define SACI_301C_THRD_MASK (0xffffffff)
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#define SACI_3020_SACI_RX_PACK_MODE (0x3020)
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#define SACI_3020_VLD_BITS_POS (0x0)
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#define SACI_3020_VLD_BITS_MASK (0xffffffff)
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#define SACI_3024_SACI_RX_OFF_WAIT_TIME (0x3024)
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#define SACI_3024_CNT_POS (0x0)
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#define SACI_3024_CNT_MASK (0xffffffff)
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#define SACI_4000_SACI_RX_FIFO_DATA (0x4000)
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#define SACI_4000_SACI_RX_FIFO_DATA_POS (0x0)
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#define SACI_4000_SACI_RX_FIFO_DATA_MASK (0xffffffff)
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#define SACI_5000_SACI_PDM_CLK_0_CTRL (0x5000)
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#define SACI_5000_CLK_DEV_POS (0x10)
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#define SACI_5000_CLK_DEV_MASK (0xfff0000)
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#define SACI_5000_DIV_CLK_EN_POS (0x5)
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#define SACI_5000_DIV_CLK_EN_MASK (0x20)
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#define SACI_5000_CLK_O_EN_POS (0x4)
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#define SACI_5000_CLK_O_EN_MASK (0x10)
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#define SACI_5000_CLK_POL_POS (0x3)
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#define SACI_5000_CLK_POL_MASK (0x8)
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#define SACI_5000_CLK_SEL_POS (0x0)
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#define SACI_5000_CLK_SEL_MASK (0x7)
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#define SACI_5004_SACI_PDM_CLK_1_CTRL (0x5004)
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#define SACI_5004_CLK_DEV_POS (0x10)
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#define SACI_5004_CLK_DEV_MASK (0xfff0000)
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#define SACI_5004_DIV_CLK_EN_POS (0x5)
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#define SACI_5004_DIV_CLK_EN_MASK (0x20)
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#define SACI_5004_CLK_O_EN_POS (0x4)
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#define SACI_5004_CLK_O_EN_MASK (0x10)
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#define SACI_5004_CLK_POL_POS (0x3)
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#define SACI_5004_CLK_POL_MASK (0x8)
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#define SACI_5004_CLK_SEL_POS (0x0)
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#define SACI_5004_CLK_SEL_MASK (0x7)
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#define SACI_5008_SACI_PDM_CTRL_0 (0x5008)
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#define SACI_5008_PDM_DMA_EN_POS (0x10)
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#define SACI_5008_PDM_DMA_EN_MASK (0x10000)
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#define SACI_5008_MODE_POS (0x0)
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#define SACI_5008_MODE_MASK (0x3)
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#define SACI_500C_SACI_PDM_CTRL_1 (0x500c)
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#define SACI_500C_PDM_DMA_EN_POS (0x10)
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#define SACI_500C_PDM_DMA_EN_MASK (0x10000)
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#define SACI_500C_MODE_POS (0x0)
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#define SACI_500C_MODE_MASK (0x3)
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#define SACI_5010_SACI_PDM_FIFO_CTRL_0 (0x5010)
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#define SACI_5010_THRD_POS (0x10)
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#define SACI_5010_THRD_MASK (0xfff0000)
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#define SACI_5010_TEST_EN_POS (0x8)
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#define SACI_5010_TEST_EN_MASK (0x100)
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#define SACI_5010_DATA_ALIGN_POS (0x1)
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#define SACI_5010_DATA_ALIGN_MASK (0x2)
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#define SACI_5010_DATA_PACK_MODE_POS (0x0)
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#define SACI_5010_DATA_PACK_MODE_MASK (0x1)
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#define SACI_5014_SACI_PDM_FIFO_CTRL_1 (0x5014)
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#define SACI_5014_THRD_POS (0x10)
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#define SACI_5014_THRD_MASK (0xfff0000)
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#define SACI_5014_TEST_EN_POS (0x8)
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#define SACI_5014_TEST_EN_MASK (0x100)
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#define SACI_5014_DATA_ALIGN_POS (0x1)
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#define SACI_5014_DATA_ALIGN_MASK (0x2)
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#define SACI_5014_DATA_PACK_MODE_POS (0x0)
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#define SACI_5014_DATA_PACK_MODE_MASK (0x1)
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#define SACI_5018_SACI_PDM_FIFO_STA_0 (0x5018)
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#define SACI_5018_FIFO_DPT_POS (0x10)
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#define SACI_5018_FIFO_DPT_MASK (0xfff0000)
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#define SACI_5018_VLD_DATA_WID_POS (0x8)
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#define SACI_5018_VLD_DATA_WID_MASK (0x3f00)
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#define SACI_5018_FULL_POS (0x1)
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#define SACI_5018_FULL_MASK (0x2)
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#define SACI_5018_EMPTY_POS (0x0)
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#define SACI_5018_EMPTY_MASK (0x1)
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#define SACI_501C_SACI_PDM_FIFO_STA_1 (0x501c)
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#define SACI_501C_FIFO_DPT_POS (0x10)
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#define SACI_501C_FIFO_DPT_MASK (0xfff0000)
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#define SACI_501C_VLD_DATA_WID_POS (0x8)
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#define SACI_501C_VLD_DATA_WID_MASK (0x3f00)
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#define SACI_501C_FULL_POS (0x1)
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#define SACI_501C_FULL_MASK (0x2)
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#define SACI_501C_EMPTY_POS (0x0)
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#define SACI_501C_EMPTY_MASK (0x1)
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#define SACI_5020_SACI_PDM_FILTER_CTRL_0 (0x5020)
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#define SACI_5020_DEC_RATE_POS (0x10)
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#define SACI_5020_DEC_RATE_MASK (0x3ff0000)
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#define SACI_5020_FLT_ORDER_POS (0x0)
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#define SACI_5020_FLT_ORDER_MASK (0x7)
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#define SACI_5024_SACI_PDM_FILTER_CTRL_1 (0x5024)
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#define SACI_5024_DEC_RATE_POS (0x10)
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#define SACI_5024_DEC_RATE_MASK (0x3ff0000)
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#define SACI_5024_FLT_ORDER_POS (0x0)
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#define SACI_5024_FLT_ORDER_MASK (0x7)
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#define SACI_5030_SACI_PDM_EN_0 (0x5030)
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#define SACI_5030_PDM_EN_POS (0x0)
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#define SACI_5030_PDM_EN_MASK (0x1)
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#define SACI_5034_SACI_PDM_EN_1 (0x5034)
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#define SACI_5034_PDM_EN_POS (0x0)
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#define SACI_5034_PDM_EN_MASK (0x1)
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#define SACI_5040_SACI_PDM_MID (0x5040)
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#define SACI_5040_SACI_PDM_MID_VALUE_POS (0x0)
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#define SACI_5040_SACI_PDM_MID_VALUE_MASK (0xffffffff)
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#define SACI_6000_SACI_PDM_CH0_FIFO_DATA (0x6000)
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#define SACI_6000_SACI_PDM_CH0_FIFO_DATA_POS (0x0)
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#define SACI_6000_SACI_PDM_CH0_FIFO_DATA_MASK (0xffffffff)
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#define SACI_6800_SACI_PDM_CH1_FIFO_DATA (0x6800)
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#define SACI_6800_SACI_PDM_CH1_FIFO_DATA_POS (0x0)
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#define SACI_6800_SACI_PDM_CH1_FIFO_DATA_MASK (0xffffffff)
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#define SACI_7000_SACI_DBG_CTRL (0x7000)
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#define SACI_7000_CLR_POS (0x1)
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#define SACI_7000_CLR_MASK (0x2)
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#define SACI_7000_LOCK_POS (0x0)
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#define SACI_7000_LOCK_MASK (0x1)
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#define SACI_7004_SACI_DBG (0x7004)
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#define SACI_7004_TXWS_N_CNT_POS (0x18)
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#define SACI_7004_TXWS_N_CNT_MASK (0xff000000)
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#define SACI_7004_TXWS_P_CNT_POS (0x10)
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#define SACI_7004_TXWS_P_CNT_MASK (0xff0000)
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#define SACI_7004_RXWS_B_CNT_POS (0x8)
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#define SACI_7004_RXWS_B_CNT_MASK (0xff00)
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#define SACI_7004_RXWS_P_CNT_POS (0x0)
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#define SACI_7004_RXWS_P_CNT_MASK (0xff)
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#define SACI_7008_SACI_DBG_1 (0x7008)
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#define SACI_7008_TX_LOAD_CNT_POS (0x18)
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#define SACI_7008_TX_LOAD_CNT_MASK (0xff000000)
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#define SACI_7008_RX_LOAD_CNT_POS (0x10)
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#define SACI_7008_RX_LOAD_CNT_MASK (0xff0000)
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#define SACI_7008_RXWS_INT_N_CNT_POS (0x8)
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#define SACI_7008_RXWS_INT_N_CNT_MASK (0xff00)
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#define SACI_7008_RXWS_INT_P_CNT_POS (0x0)
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#define SACI_7008_RXWS_INT_P_CNT_MASK (0xff)
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#define SACI_700C_SACI_DEBUG2 (0x700c)
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#define SACI_700C_PDM0_LOAD_CNT_POS (0x0)
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#define SACI_700C_PDM0_LOAD_CNT_MASK (0xff)
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#endif // SDRV_SCAI_REGS_H_
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