661 lines
20 KiB
C
661 lines
20 KiB
C
/**
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* @file sdrv_i2c_drv.c
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* @brief sdrv i2c driver function file.
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*
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* @Copyright (c) 2022 Semidrive Semiconductor.
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* @All rights reserved.
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**/
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#include <debug.h>
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#include <udelay/udelay.h>
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#include <sdrv_i2c.h>
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#include "irq.h"
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#include "sdrv_i2c_reg.h"
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#define i2c_min(a, b) ((a) < (b) ? a : b)
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/**
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* @brief I2c check error type
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*
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* @param[in] base i2c controller instance pointer
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* @param[in] errcode err code storage variable pointer
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* @param[in] id i2c bus num
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* @param[in] int0_stat int0 register value
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* @param[in] idx local err flag num
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*
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* @return SDRV_I2CDRV_TRANS_NAK/SDRV_I2CDRV_TRANS_ERR
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*/
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static status_t sdrv_i2c_check_err(paddr_t base, uint32_t *errcode,
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uint32_t id, uint32_t int0_stat, uint32_t idx)
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{
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status_t ret;
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uint32_t psr0_stat;
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psr0_stat = sdrv_i2c_get_psr_stat(base, I2C_PSR0);
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if ((psr0_stat & 0xff) == 0x27)
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ret = SDRV_I2CDRV_TRANS_NAK;
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else {
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ssdk_printf(SSDK_CRIT, "i2c%u err%u int0=%x, psr0=%x\r\n",
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id, idx, int0_stat, psr0_stat);
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*errcode = psr0_stat;
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sdrv_i2c_reset(base);
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ret = SDRV_I2CDRV_TRANS_ERR;
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}
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return ret;
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}
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/**
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* @brief I2c write data to slave in polling mode
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*
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* @param[in] base i2c controller instance pointer
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* @param[in] id i2c controller instance num
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* @param[in] mctrl i2c controller instance pointer
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* @param[in] timeout timeout in milliseconds to wait (0 = wait forever)
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*
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* @return SDRV_I2CDRV_TRANS_OK
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* SDRV_I2CDRV_TRANS_GO
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* SDRV_I2CDRV_TRANS_ERR
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* SDRV_I2CDRV_TRANS_NAK
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* SDRV_I2CDRV_TRANS_TIMEOUT
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*/
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static status_t sdrv_i2c_pwrite(paddr_t base, uint32_t id,
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sdrv_i2cdrv_mctrl_t *mctrl,
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uint32_t timeout)
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{
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uint8_t len = 0;
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uint8_t flen = 0;
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const uint32_t retry_delay = 10; /* us */
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uint64_t retry_times = (uint64_t)timeout * 1000 / retry_delay;
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uint64_t scnt = 100000UL / retry_delay;
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uint32_t int0_stat = 0;
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uint8_t *wbuf = mctrl->buf;
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uint16_t wlen = mctrl->len;
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while (wlen) {
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int0_stat = sdrv_i2c_get_int_stat(base, I2C_INTR0);
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if (int0_stat & SDRV_I2C_INT0_ERR_STAT)
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return sdrv_i2c_check_err(base, &mctrl->trans_errcode,
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id, int0_stat, 1);
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flen = (uint8_t)sdrv_i2c_get_wspace(base);
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if (flen > 0) {
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len = i2c_min(flen, wlen);
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wlen -= len;
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while (len--)
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sdrv_i2c_send_data(base, *wbuf++);
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}
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else if (timeout > 0) {
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if (retry_times--) {
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udelay(retry_delay);
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continue;
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}
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else {
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ssdk_printf(SSDK_CRIT, "i2c%u write retry time runs out\r\n", id);
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return SDRV_I2CDRV_TRANS_TIMEOUT;
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}
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}
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}
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if (timeout > 0) {
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if (retry_times > 0)
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scnt = retry_times;
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else
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scnt = 1;
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}
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while (scnt--) {
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int0_stat = sdrv_i2c_get_int_stat(base, I2C_INTR0);
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if (int0_stat & SDRV_I2C_INT0_APBCMDDONE) {
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return SDRV_I2CDRV_TRANS_OK;
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}
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else if (int0_stat & SDRV_I2C_INT0_ERR_STAT) {
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return sdrv_i2c_check_err(base, &mctrl->trans_errcode,
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id, int0_stat, 2);
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}
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else if (scnt <= 1) {
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ssdk_printf(SSDK_CRIT, "i2c%u pwerr may hold by slave\r\n", id);
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return SDRV_I2CDRV_TRANS_TIMEOUT;
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}
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else
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udelay(retry_delay);
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}
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return SDRV_I2CDRV_TRANS_GO;
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}
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/**
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* @brief I2c read data from slave in polling mode
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*
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* @param[in] base i2c controller instance pointer
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* @param[in] id i2c controller instance num
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* @param[in] mctrl i2c controller instance pointer
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* @param[in] timeout timeout in milliseconds to wait (0 = wait forever)
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*
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* @return SDRV_I2CDRV_TRANS_OK
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* SDRV_I2CDRV_TRANS_GO
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* SDRV_I2CDRV_TRANS_ERR
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* SDRV_I2CDRV_TRANS_NAK
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* SDRV_I2CDRV_TRANS_TIMEOUT
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*/
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static status_t sdrv_i2c_pread(paddr_t base, uint32_t id,
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sdrv_i2cdrv_mctrl_t *mctrl,
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uint32_t timeout)
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{
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uint8_t len = 0;
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uint8_t flen = 0;
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const uint32_t retry_delay = 10; /* us */
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uint64_t retry_times = (uint64_t)timeout * 1000 / retry_delay;
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uint64_t scnt = 100000UL / retry_delay;
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uint32_t int0_stat = 0;
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uint8_t *rbuf = mctrl->buf;
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uint16_t rlen = mctrl->len;
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while (rlen) {
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int0_stat = sdrv_i2c_get_int_stat(base, I2C_INTR0);
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if (int0_stat & SDRV_I2C_INT0_ERR_STAT)
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return sdrv_i2c_check_err(base, &mctrl->trans_errcode,
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id, int0_stat, 3);
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flen = (uint8_t)sdrv_i2c_get_rspace(base);
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if (flen > 0) {
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len = i2c_min(flen, rlen);
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rlen -= len;
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while (len--)
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*rbuf++ = sdrv_i2c_recv_data(base);
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}
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else if (timeout > 0) {
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if (retry_times--) {
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udelay(retry_delay);
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continue;
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}
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else {
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ssdk_printf(SSDK_CRIT, "i2c%u read retry time runs out\r\n", id);
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return SDRV_I2CDRV_TRANS_TIMEOUT;
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}
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}
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}
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if (timeout > 0) {
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if (retry_times > 0)
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scnt = retry_times;
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else
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scnt = 1;
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}
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while (scnt--) {
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int0_stat = sdrv_i2c_get_int_stat(base, I2C_INTR0);
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if (int0_stat & SDRV_I2C_INT0_APBCMDDONE) {
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return SDRV_I2CDRV_TRANS_OK;
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}
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else if (int0_stat & SDRV_I2C_INT0_ERR_STAT) {
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return sdrv_i2c_check_err(base, &mctrl->trans_errcode,
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id, int0_stat, 4);
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}
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else if (scnt <= 1) {
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ssdk_printf(SSDK_CRIT, "i2c%u prerr may hold by slave\r\n", id);
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return SDRV_I2CDRV_TRANS_TIMEOUT;
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}
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else
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udelay(retry_delay);
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}
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return SDRV_I2CDRV_TRANS_GO;
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}
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/**
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* @brief I2c transfer init
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*
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* @param[in] base i2c controller address
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*
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* @return SDRV_STATUS_OK/SDRV_STATUS_FAIL
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*/
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static status_t sdrv_i2c_xfer_init(paddr_t base)
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{
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int cnt = 100;
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sdrv_i2c_set_cmdcsr(base, I2C_CMDCSR0, 0xA5C3);
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sdrv_i2c_clear_fifo(base);
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do {
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if (sdrv_i2c_get_fifo_empty_stat(base))
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return SDRV_STATUS_OK;
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udelay(10);
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} while (cnt--);
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return SDRV_STATUS_FAIL;
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}
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/**
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* @brief I2c driver real transfer function entry
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* init the controller with client configer info(speed/addr/len/need_stop...)
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*
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* @param[in] ctrl i2c controller instance pointer
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* @param[in] timeout timeout in milliseconds to wait (0 = wait forever)
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*
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* @return SDRV_STATUS_OK/SDRV_STATUS_FAIL
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*/
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static status_t sdrv_i2c_xfer(sdrv_i2c_t *ctrl, uint32_t timeout)
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{
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status_t ret;
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uint32_t int0_mask;
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sdrv_i2c_cfg_t *cfg = ctrl->cfg;
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sdrv_i2cdrv_mctrl_t *mctrl = &ctrl->mctrl;
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mctrl->trans_stat = SDRV_I2CDRV_TRANS_GO;
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mctrl->trans_errcode = 0;
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if (!ctrl->cfg->inited) {
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ssdk_printf(SSDK_CRIT, "i2c%u not init\r\n", ctrl->cfg->id);
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mctrl->trans_stat = SDRV_I2CDRV_TRANS_ABORT;
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return SDRV_STATUS_FAIL;
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}
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sdrv_i2c_disable_int(cfg->base);
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ret = sdrv_i2c_xfer_init(cfg->base);
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if (ret == SDRV_STATUS_FAIL) {
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ssdk_printf(SSDK_CRIT, "i2c%u xfer init fail\r\n", cfg->id);
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mctrl->trans_stat = SDRV_I2CDRV_TRANS_ABORT;
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return ret;
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}
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sdrv_i2c_clear_int(cfg->base);
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sdrv_i2c_set_cmdcsr(cfg->base, I2C_CMDCSR2,
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mctrl->slave_addr | (mctrl->read_flag << 11) |
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(mctrl->len << 16));
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if (mctrl->need_stop)
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sdrv_i2c_set_cmdcsr(cfg->base, I2C_CMDCSR0, 0xA53C | (0x1 << 30));
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else
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sdrv_i2c_set_cmdcsr(cfg->base, I2C_CMDCSR0, 0xA53C | (0x0 << 30));
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if (cfg->tsmode == SDRV_I2CDRV_POLL) {
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if (mctrl->read_flag)
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mctrl->trans_stat = sdrv_i2c_pread(cfg->base, cfg->id, mctrl, timeout);
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else
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mctrl->trans_stat = sdrv_i2c_pwrite(cfg->base, cfg->id, mctrl, timeout);
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}
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else {
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if (mctrl->read_flag)
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int0_mask = SDRV_I2C_INT0_DEFAULT_MASK | SDRV_I2C_INT0_RXFWF;
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else
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int0_mask = SDRV_I2C_INT0_DEFAULT_MASK | SDRV_I2C_INT0_TXFWE;
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sdrv_i2c_unmask_int(cfg->base, I2C_INTEN0, int0_mask);
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}
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return SDRV_STATUS_OK;
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}
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/**
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* @brief I2c master mode interrupt handler for data send/receive and
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* transfer status check
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*
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* @param[in] irq i2c controller irq num
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* @param[in] arg i2c ctrl instance get from irq register
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*
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* @return 0
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*/
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static int sdrv_i2c_master_irq_handler(uint32_t irq, void *arg)
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{
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uint16_t len = 0;
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uint16_t flen = 0;
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uint8_t *buf = NULL;
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uint32_t int0_stat = 0;
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sdrv_i2c_t *ctrl = arg;
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sdrv_i2c_cfg_t *cfg = ctrl->cfg;
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sdrv_i2cdrv_mctrl_t *mctrl = &ctrl->mctrl;
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int0_stat = sdrv_i2c_get_int_stat(cfg->base, I2C_INTR0);
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sdrv_i2c_clear_int_bits(cfg->base, I2C_INTR0, int0_stat);
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if (int0_stat & SDRV_I2C_INT0_APBCMDDONE) {
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mctrl->trans_stat = SDRV_I2CDRV_TRANS_OK;
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if (mctrl->cb)
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mctrl->cb(ctrl, mctrl->cb_param, mctrl->trans_stat);
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}
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else if (int0_stat & SDRV_I2C_INT0_ERR_STAT) {
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mctrl->trans_stat = sdrv_i2c_check_err(cfg->base, &mctrl->trans_errcode,
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cfg->id, int0_stat, 0);
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if (mctrl->cb)
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mctrl->cb(ctrl, mctrl->cb_param, mctrl->trans_stat);
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sdrv_i2c_disable_int(cfg->base);
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return 0;
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}
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buf = mctrl->buf + mctrl->cur_len;
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if (mctrl->read_flag) {
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flen = sdrv_i2c_get_rspace(cfg->base);
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len = i2c_min(flen, mctrl->len - mctrl->cur_len);
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mctrl->cur_len += len;
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while (len--)
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*buf++ = sdrv_i2c_recv_data(cfg->base);
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}
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else {
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flen = sdrv_i2c_get_wspace(cfg->base);
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len = i2c_min(flen, mctrl->len - mctrl->cur_len);
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mctrl->cur_len += len;
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while (len--)
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sdrv_i2c_send_data(cfg->base, *buf++);
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}
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if (mctrl->cur_len >= mctrl->len)
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sdrv_i2c_unmask_int(cfg->base, I2C_INTEN0, SDRV_I2C_INT0_DEFAULT_MASK);
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if (int0_stat & SDRV_I2C_INT0_APBCMDDONE)
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sdrv_i2c_disable_int(cfg->base);
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return 0;
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}
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/**
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* @brief Set bus stat(only applicable for master).
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* @this api will abandon,please use
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* sdrv_i2c_lock_bus/sdrv_i2c_unlock_bus instead
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*
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* @param[in] ctrl i2c controller instance pointer
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* @param[in] bus_stat bus stat to be set
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*
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* @return SDRV_STATUS_OK
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*/
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status_t sdrv_i2c_set_bus_stat(sdrv_i2c_t *ctrl,
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sdrv_i2cdrv_bus_stat_t bus_stat)
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{
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ASSERT(ctrl != NULL);
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ASSERT(ctrl->cfg != NULL);
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ASSERT(ctrl->cfg->opmode == SDRV_I2CDRV_MASTER);
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ctrl->cfg->bus_stat = bus_stat;
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return SDRV_STATUS_OK;
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}
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/**
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* @brief Get bus stat(only applicable for master).
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* @this api will abandon,please use
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* sdrv_i2c_lock_bus/sdrv_i2c_unlock_bus instead
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*
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* @param[in] ctrl i2c controller instance pointer
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*
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* @return SDRV_I2CDRV_BUS_IDLE/SDRV_I2CDRV_BUS_BUSY
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*/
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sdrv_i2cdrv_bus_stat_t sdrv_i2c_get_bus_stat(sdrv_i2c_t *ctrl)
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{
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ASSERT(ctrl != NULL);
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ASSERT(ctrl->cfg != NULL);
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ASSERT(ctrl->cfg->opmode == SDRV_I2CDRV_MASTER);
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return ctrl->cfg->bus_stat;
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}
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/**
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* @brief Lock bus stat(only applicable for master).
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*
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* @param[in] ctrl i2c controller instance pointer
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*
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* @return SDRV_STATUS_OK/SDRV_STATUS_FAIL
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*/
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status_t sdrv_i2c_lock_bus(sdrv_i2c_t *ctrl)
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{
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ASSERT(ctrl != NULL);
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ASSERT(ctrl->cfg != NULL);
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ASSERT(ctrl->cfg->opmode == SDRV_I2CDRV_MASTER);
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irq_state_t irq_stat;
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status_t ret = SDRV_STATUS_FAIL;
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irq_stat = arch_irq_save();
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if (ctrl->cfg->bus_stat == SDRV_I2CDRV_BUS_IDLE) {
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ctrl->cfg->bus_stat = SDRV_I2CDRV_BUS_BUSY;
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ret = SDRV_STATUS_OK;
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}
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arch_irq_restore(irq_stat);
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return ret;
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}
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/**
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* @brief Unlock bus stat(only applicable for master).
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*
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* @param[in] ctrl i2c controller instance pointer
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*
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* @return SDRV_STATUS_OK
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*/
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status_t sdrv_i2c_unlock_bus(sdrv_i2c_t *ctrl)
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{
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ASSERT(ctrl != NULL);
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ASSERT(ctrl->cfg != NULL);
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ASSERT(ctrl->cfg->opmode == SDRV_I2CDRV_MASTER);
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irq_state_t irq_stat;
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irq_stat = arch_irq_save();
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ctrl->cfg->bus_stat = SDRV_I2CDRV_BUS_IDLE;
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arch_irq_restore(irq_stat);
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return SDRV_STATUS_OK;
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}
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/**
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* @brief Init the i2c controller.
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*
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* @param[in] ctrl i2c controller instance pointer
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*
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* @return SDRV_STATUS_OK/SDRV_STATUS_FAIL
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*/
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status_t sdrv_i2c_init_ctrl(sdrv_i2c_t *ctrl)
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{
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ASSERT(ctrl != NULL);
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ASSERT(ctrl->cfg != NULL);
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if (ctrl->cfg->inited == 1)
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return SDRV_STATUS_OK;
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sdrv_i2c_disable_int(ctrl->cfg->base);
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sdrv_i2c_clear_fifo(ctrl->cfg->base);
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sdrv_i2c_clear_int(ctrl->cfg->base);
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sdrv_i2c_reset(ctrl->cfg->base);
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sdrv_i2c_set_watermark(ctrl->cfg->base, SDRV_I2C_RXTX_WML);
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if (ctrl->cfg->speed == SDRV_I2CDRV_SSPEED)
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|
sdrv_i2c_set_timing(ctrl->cfg->base, ctrl->cfg->clk, 0);
|
|
else if (ctrl->cfg->speed == SDRV_I2CDRV_FSPEED)
|
|
sdrv_i2c_set_timing(ctrl->cfg->base, ctrl->cfg->clk, 1);
|
|
else if (ctrl->cfg->speed == SDRV_I2CDRV_PSPEED)
|
|
sdrv_i2c_set_timing(ctrl->cfg->base, ctrl->cfg->clk, 2);
|
|
else if (ctrl->cfg->speed == SDRV_I2CDRV_HSPEED)
|
|
sdrv_i2c_set_timing(ctrl->cfg->base, ctrl->cfg->clk, 3);
|
|
else if (ctrl->cfg->speed == SDRV_I2CDRV_USPEED)
|
|
sdrv_i2c_set_timing(ctrl->cfg->base, ctrl->cfg->clk, 4);
|
|
|
|
if (ctrl->cfg->speed == SDRV_I2CDRV_HSPEED)
|
|
sdrv_i2c_set_speed(ctrl->cfg->base, ctrl->cfg->clk, SDRV_I2C_HSPEED);
|
|
else if (ctrl->cfg->speed == SDRV_I2CDRV_USPEED)
|
|
sdrv_i2c_set_speed(ctrl->cfg->base, ctrl->cfg->clk, SDRV_I2C_USPEED);
|
|
else
|
|
sdrv_i2c_set_speed(ctrl->cfg->base, ctrl->cfg->clk, SDRV_I2C_NSPEED);
|
|
|
|
if (ctrl->cfg->opmode == SDRV_I2CDRV_MASTER) {
|
|
sdrv_i2c_set_opmode(ctrl->cfg->base, SDRV_I2C_MASTER);
|
|
irq_attach(ctrl->cfg->irq, sdrv_i2c_master_irq_handler, ctrl);
|
|
irq_enable(ctrl->cfg->irq);
|
|
}
|
|
else {
|
|
ssdk_printf(SSDK_CRIT, "i2c%u opmode err\r\n", ctrl->cfg->id);
|
|
return SDRV_STATUS_FAIL;
|
|
}
|
|
|
|
ctrl->cfg->inited = 1;
|
|
return SDRV_STATUS_OK;
|
|
}
|
|
|
|
/**
|
|
* @brief Write data to slave device use poll blocking format
|
|
*
|
|
* @param[in] ctrl i2c controller instance pointer
|
|
* @param[in] addr slave device 7bit addr not include LSB read/write bit
|
|
* @param[in] wbuf point to data buf for send
|
|
* @param[in] wlen data buf len
|
|
* @param[in] timeout timeout in milliseconds to wait (0 = wait forever)
|
|
* @param[in] need_stop whether send stop signal or hold sda after finish write
|
|
*
|
|
* @return SDRV_STATUS_OK/SDRV_STATUS_FAIL
|
|
*/
|
|
status_t sdrv_i2c_write(sdrv_i2c_t *ctrl, uint16_t addr,
|
|
uint8_t *wbuf, uint16_t wlen,
|
|
uint32_t timeout, bool need_stop)
|
|
{
|
|
ASSERT(ctrl != NULL);
|
|
ASSERT(ctrl->cfg != NULL);
|
|
ASSERT(wbuf != NULL);
|
|
ASSERT(ctrl->cfg->opmode == SDRV_I2CDRV_MASTER);
|
|
|
|
ctrl->mctrl.slave_addr = addr;
|
|
ctrl->mctrl.buf = wbuf;
|
|
ctrl->mctrl.len = wlen;
|
|
ctrl->mctrl.read_flag = 0x0;
|
|
ctrl->mctrl.need_stop = need_stop;
|
|
ctrl->mctrl.cb = NULL;
|
|
ctrl->mctrl.cur_len = 0;
|
|
ctrl->cfg->tsmode = SDRV_I2CDRV_POLL;
|
|
|
|
return sdrv_i2c_xfer(ctrl, timeout);
|
|
}
|
|
|
|
/**
|
|
* @brief Read data from slave device use poll blocking format
|
|
*
|
|
* @param[in] ctrl i2c controller instance pointer
|
|
* @param[in] addr slave device 7bit addr not include LSB read/write bit
|
|
* @param[out] rbuf point to data buf for receive
|
|
* @param[in] rlen data buf len
|
|
* @param[in] timeout timeout in milliseconds to wait (0 = wait forever)
|
|
* @param[in] need_stop whether send stop signal or hold sda after finish read
|
|
*
|
|
* @return SDRV_STATUS_OK/SDRV_STATUS_FAIL
|
|
*/
|
|
status_t sdrv_i2c_read(sdrv_i2c_t *ctrl, uint16_t addr,
|
|
uint8_t *rbuf, uint16_t rlen,
|
|
uint32_t timeout, bool need_stop)
|
|
{
|
|
ASSERT(ctrl != NULL);
|
|
ASSERT(ctrl->cfg != NULL);
|
|
ASSERT(rbuf != NULL);
|
|
ASSERT(ctrl->cfg->opmode == SDRV_I2CDRV_MASTER);
|
|
|
|
ctrl->mctrl.slave_addr = addr;
|
|
ctrl->mctrl.buf = rbuf;
|
|
ctrl->mctrl.len = rlen;
|
|
ctrl->mctrl.read_flag = 0x1;
|
|
ctrl->mctrl.need_stop = need_stop;
|
|
ctrl->mctrl.cb = NULL;
|
|
ctrl->mctrl.cur_len = 0;
|
|
ctrl->cfg->tsmode = SDRV_I2CDRV_POLL;
|
|
|
|
return sdrv_i2c_xfer(ctrl, timeout);
|
|
}
|
|
|
|
/**
|
|
* @brief Write data to slave device use interrupt non-blocking format
|
|
*
|
|
* @param[in] ctrl i2c controller instance pointer
|
|
* @param[in] addr slave device 7bit addr not include LSB read/write bit
|
|
* @param[in] wbuf point to data buf for send
|
|
* @param[in] wlen data buf len
|
|
* @param[in] need_stop whether send stop signal or hold sda after finish write
|
|
* @param[in] cb callback function pointer
|
|
* @param[in] cb_param callback user parameter
|
|
*
|
|
* @return SDRV_STATUS_OK/SDRV_STATUS_FAIL
|
|
*/
|
|
status_t sdrv_i2c_write_async(sdrv_i2c_t *ctrl,
|
|
uint16_t addr, uint8_t *wbuf, uint16_t wlen,
|
|
bool need_stop, sdrv_i2c_cb_t cb, void *cb_param)
|
|
{
|
|
ASSERT(ctrl != NULL);
|
|
ASSERT(ctrl->cfg != NULL);
|
|
ASSERT(wbuf != NULL);
|
|
ASSERT(ctrl->cfg->opmode == SDRV_I2CDRV_MASTER);
|
|
|
|
ctrl->mctrl.slave_addr = addr;
|
|
ctrl->mctrl.buf = wbuf;
|
|
ctrl->mctrl.len = wlen;
|
|
ctrl->mctrl.read_flag = 0x0;
|
|
ctrl->mctrl.need_stop = need_stop;
|
|
ctrl->mctrl.cb = cb;
|
|
ctrl->mctrl.cb_param = cb_param;
|
|
ctrl->mctrl.cur_len = 0;
|
|
ctrl->cfg->tsmode = SDRV_I2CDRV_INTP;
|
|
|
|
return sdrv_i2c_xfer(ctrl, 0);
|
|
}
|
|
|
|
/**
|
|
* @brief Read data from slave device use interrupt non-blocking format
|
|
*
|
|
* @param[in] ctrl i2c controller instance pointer
|
|
* @param[in] addr slave device 7bit addr not include LSB read/write bit
|
|
* @param[out] rbuf point to data buf for receive
|
|
* @param[in] rlen data buf len
|
|
* @param[in] need_stop whether send stop signal or hold sda after complete read
|
|
* @param[in] cb callback function pointer
|
|
* @param[in] cb_param callback user parameter
|
|
*
|
|
* @return SDRV_STATUS_OK/SDRV_STATUS_FAIL
|
|
*/
|
|
status_t sdrv_i2c_read_async(sdrv_i2c_t *ctrl,
|
|
uint16_t addr, uint8_t *rbuf, uint16_t rlen,
|
|
bool need_stop, sdrv_i2c_cb_t cb, void *cb_param)
|
|
{
|
|
ASSERT(ctrl != NULL);
|
|
ASSERT(ctrl->cfg != NULL);
|
|
ASSERT(rbuf != NULL);
|
|
ASSERT(ctrl->cfg->opmode == SDRV_I2CDRV_MASTER);
|
|
|
|
ctrl->mctrl.slave_addr = addr;
|
|
ctrl->mctrl.buf = rbuf;
|
|
ctrl->mctrl.len = rlen;
|
|
ctrl->mctrl.read_flag = 0x1;
|
|
ctrl->mctrl.need_stop = need_stop;
|
|
ctrl->mctrl.cb = cb;
|
|
ctrl->mctrl.cb_param = cb_param;
|
|
ctrl->mctrl.cur_len = 0;
|
|
ctrl->cfg->tsmode = SDRV_I2CDRV_INTP;
|
|
|
|
return sdrv_i2c_xfer(ctrl, 0);
|
|
}
|
|
|
|
/**
|
|
* @brief Get transfer stat(only applicable for master).
|
|
*
|
|
* @param[in] ctrl i2c controller instance pointer
|
|
*
|
|
* @return SDRV_I2CDRV_TRANS_OK
|
|
* SDRV_I2CDRV_TRANS_GO
|
|
* SDRV_I2CDRV_TRANS_ERR
|
|
* SDRV_I2CDRV_TRANS_NAK
|
|
* SDRV_I2CDRV_TRANS_ABORT
|
|
* SDRV_I2CDRV_TRANS_TIMEOUT
|
|
*/
|
|
status_t sdrv_i2c_get_trans_stat(sdrv_i2c_t *ctrl)
|
|
{
|
|
ASSERT(ctrl != NULL);
|
|
ASSERT(ctrl->cfg != NULL);
|
|
ASSERT(ctrl->cfg->opmode == SDRV_I2CDRV_MASTER);
|
|
|
|
return ctrl->mctrl.trans_stat;
|
|
}
|
|
|