384 lines
22 KiB
C
384 lines
22 KiB
C
/**
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* @file scr_hw.h
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* @brief Status and Controller Register (SCR) signal header file.
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*
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* @copyright Copyright (c) 2022 Semidrive Semiconductor.
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* All rights reserved.
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*/
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#ifndef _SCR_HW_H_
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#define _SCR_HW_H_
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#define SCR_SF_EFUSEC_MANU_CFG_87_64 {TYPE_RO, 32, 24}
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#define SCR_SF_EFUSEC_MISC_CFG_7 {TYPE_RO, 56, 1}
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#define SCR_SF_EFUSEC_MANU_CFG_95 {TYPE_RO, 57, 1}
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#define SCR_SF_EFUSEC_FA_CFG_0 {TYPE_RO, 58, 1}
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#define SCR_SF_FAB_SF_M_F_0_I_MAINNOPENDINGTRANS {TYPE_RO, 64, 1}
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#define SCR_SF_FAB_SF_M_F_1_I_MAINNOPENDINGTRANS {TYPE_RO, 65, 1}
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#define SCR_SF_FAB_SF_M_F_2_I_MAINNOPENDINGTRANS {TYPE_RO, 66, 1}
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#define SCR_SF_FAB_SF_M_F_3_I_MAINNOPENDINGTRANS {TYPE_RO, 67, 1}
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#define SCR_SF_FAB_SF_M_F_4_I_MAINNOPENDINGTRANS {TYPE_RO, 68, 1}
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#define SCR_SF_FAB_SF_M_F_5_I_MAINNOPENDINGTRANS {TYPE_RO, 69, 1}
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#define SCR_SF_FAB_SF_M_F_6_I_MAINNOPENDINGTRANS {TYPE_RO, 70, 1}
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#define SCR_SF_FAB_SF_M_F_GPV_I_MAINNOPENDINGTRANS {TYPE_RO, 71, 1}
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#define SCR_SF_FAB_SF_S_F_0_T_MAINNOPENDINGTRANS {TYPE_RO, 72, 1}
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#define SCR_SF_FAB_SF_S_F_1_T_MAINNOPENDINGTRANS {TYPE_RO, 73, 1}
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#define SCR_SF_FAB_SF_S_F_3_I_MAINNOPENDINGTRANS {TYPE_RO, 75, 1}
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#define SCR_SF_FAB_SF_S_F_4_I_MAINNOPENDINGTRANS {TYPE_RO, 76, 1}
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#define SCR_SF_FAB_SF_S_F_5_I_MAINNOPENDINGTRANS {TYPE_RO, 77, 1}
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#define SCR_SF_FAB_SF_S_F_6_I_MAINNOPENDINGTRANS {TYPE_RO, 78, 1}
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#define SCR_SF_FAB_SF_S_F_7_I_MAINNOPENDINGTRANS {TYPE_RO, 79, 1}
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#define SCR_SF_FAB_SF_SVREG_T_MAINNOPENDINGTRANS {TYPE_RO, 80, 1}
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#define SCR_SF_FAB_SF_SVREG_MAINNOPENDINGTRANS {TYPE_RO, 81, 1}
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#define SCR_SF_FAB_AP_M_A_0_I_MAINNOPENDINGTRANS {TYPE_RO, 82, 1}
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#define SCR_SF_FAB_AP_M_A_1_I_MAINNOPENDINGTRANS {TYPE_RO, 83, 1}
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#define SCR_SF_FAB_AP_M_A_2_I_MAINNOPENDINGTRANS {TYPE_RO, 84, 1}
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#define SCR_SF_FAB_AP_M_A_3_I_MAINNOPENDINGTRANS {TYPE_RO, 85, 1}
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#define SCR_SF_FAB_AP_M_A_4_I_MAINNOPENDINGTRANS {TYPE_RO, 86, 1}
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#define SCR_SF_FAB_AP_M_A_5_I_MAINNOPENDINGTRANS {TYPE_RO, 87, 1}
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#define SCR_SF_FAB_AP_M_A_GPV_I_MAINNOPENDINGTRANS {TYPE_RO, 88, 1}
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#define SCR_SF_FAB_AP_S_A_0_T_MAINNOPENDINGTRANS {TYPE_RO, 89, 1}
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#define SCR_SF_FAB_AP_SVREG_T_MAINNOPENDINGTRANS {TYPE_RO, 90, 1}
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#define SCR_SF_FAB_AP_SVREG_MAINNOPENDINGTRANS {TYPE_RO, 91, 1}
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#define SCR_SF_EFUSEC_FUSE_READY {TYPE_RO, 96, 1}
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#define SCR_SF_EFUSEC_FUSE_LATCHED_PARTIAL {TYPE_RO, 97, 1}
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#define SCR_SF_ANA_SF_AMUX_REF_P_CSEL_OUT_3_0 {TYPE_RO, 128, 4}
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#define SCR_SF_ANA_SF_AMUX_REF_N_CSEL_OUT_3_0 {TYPE_RO, 132, 4}
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#define SCR_SF_CR5_SF_FPIXC0 {TYPE_RO, 160, 1}
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#define SCR_SF_CR5_SF_FPOFC0 {TYPE_RO, 161, 1}
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#define SCR_SF_CR5_SF_FPUFC0 {TYPE_RO, 162, 1}
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#define SCR_SF_CR5_SF_FPIOC0 {TYPE_RO, 163, 1}
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#define SCR_SF_CR5_SF_FPDZC0 {TYPE_RO, 164, 1}
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#define SCR_SF_CR5_SF_FPIDC0 {TYPE_RO, 165, 1}
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#define SCR_SF_HV_DCDC_TGO2SAF_O_BUF_0 {TYPE_RO, 192, 1}
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#define SCR_SF_HV_DCDC_TGO2SAF_O_BUF_1 {TYPE_RO, 193, 1}
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#define SCR_SF_DMA_SF_MEM_AR_CMD_FIFO0_MEM_EMA_6_0 {TYPE_RO, 224, 7}
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#define SCR_SF_DMA_SF_MEM_AW_CMD_FIFO0_MEM_EMA_6_0 {TYPE_RO, 231, 7}
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#define SCR_SF_DMA_SF_MEM_AR_CMD_FIFO1_MEM_EMA_6_0 {TYPE_RO, 238, 7}
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#define SCR_SF_DMA_SF_MEM_AW_CMD_FIFO1_MEM_EMA_6_0 {TYPE_RO, 245, 7}
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#define SCR_SF_SCR_IRAM1_ECC_DISABLE {TYPE_L16, 0, 1}
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#define SCR_SF_REMAP_CR5_SF_AW_ADDR_OFFSET_19_0 {TYPE_L31, 0, 20}
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#define SCR_SF_SCR_REMAP_CR5_SF_REMAP_EN {TYPE_L31, 20, 1}
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#define SCR_SF_REMAP_CR5_SF_AR_ADDR_OFFSET_19_0 {TYPE_L31, 0, 20}
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#define SCR_SF_REMAP_CR5_SF_AR_REMAP_EN {TYPE_L31, 20, 1}
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#define SCR_SF_SCR_CR5_SF_DBGEN0 {TYPE_L31, 21, 1}
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#define SCR_SF_SCR_CR5_SF_NIDEN0 {TYPE_L31, 22, 1}
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#define SCR_SF_XSPI1_SRC_CFG_SWAP {TYPE_L31, 32, 1}
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#define SCR_SF_XSPI1_SRC_CFG_PARALLEL_MODE {TYPE_L31, 33, 1}
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#define SCR_SF_XSPI1_LOCKSTEP_DISABLE {TYPE_L31, 34, 1}
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#define SCR_SF_DMA_SF_LOCKSTEP_DISABLE {TYPE_L31, 64, 1}
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#define SCR_SF_SEIP_KEY_SEC_STORAGE_SCR_1_0 {TYPE_L31, 96, 2}
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#define SCR_SF_REMAP_CR5_SF_AW_IRQ_EN {TYPE_RW, 0, 1}
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#define SCR_SF_REMAP_CR5_SF_AR_IRQ_EN {TYPE_RW, 1, 1}
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#define SCR_SF_REMAP_CR5_SF_AW_UNCOR_IRQ_CLR {TYPE_RW, 2, 1}
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#define SCR_SF_REMAP_CR5_SF_AR_UNCOR_IRQ_CLR {TYPE_RW, 3, 1}
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#define SCR_SF_ETMR1_LP_MODE {TYPE_RW, 32, 1}
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#define SCR_SF_ETMR2_LP_MODE {TYPE_RW, 64, 1}
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#define SCR_SF_ANA_SF_CFG_AMUX_ADC1_CH5N_CSEL_3 {TYPE_RW, 96, 1}
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#define SCR_SF_ANA_SF_CFG_AMUX_ADC1_CH5P_CSEL_3 {TYPE_RW, 97, 1}
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#define SCR_SF_ANA_SF_CFG_AMUX_ADC2_CH4N_CSEL_3 {TYPE_RW, 98, 1}
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#define SCR_SF_ANA_SF_CFG_AMUX_ADC2_CH4P_CSEL_3 {TYPE_RW, 99, 1}
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#define SCR_SF_ANA_SF_CFG_AMUX_ADC2_CH5N_CSEL_3 {TYPE_RW, 100, 1}
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#define SCR_SF_ANA_SF_CFG_AMUX_ADC2_CH5P_CSEL_3 {TYPE_RW, 101, 1}
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#define SCR_SF_ANA_SF_CFG_AMUX_ADC2_CH6N_CSEL_3 {TYPE_RW, 102, 1}
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#define SCR_SF_ANA_SF_CFG_AMUX_ADC3_CH5N_CSEL_3 {TYPE_RW, 103, 1}
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#define SCR_SF_ANA_SF_CFG_AMUX_ADC3_CH5P_CSEL_3 {TYPE_RW, 104, 1}
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#define SCR_SF_ANA_SF_CFG_AMUX_ACMP1_CH5N_CSEL_3 {TYPE_RW, 105, 1}
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#define SCR_SF_ANA_SF_CFG_AMUX_ACMP1_CH5P_CSEL_3 {TYPE_RW, 106, 1}
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#define SCR_SF_ANA_SF_CFG_AMUX_ACMP2_CH6N_CSEL_3 {TYPE_RW, 107, 1}
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#define SCR_SF_ANA_SF_CFG_AMUX_ACMP2_CH6P_CSEL_3 {TYPE_RW, 108, 1}
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#define SCR_SF_ANA_SF_CFG_AMUX_ACMP3_CH5N_CSEL_3 {TYPE_RW, 109, 1}
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#define SCR_SF_ANA_SF_CFG_AMUX_ACMP3_CH5P_CSEL_3 {TYPE_RW, 110, 1}
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#define SCR_SF_ANA_SF_CFG_AMUX_ACMP4_CH6N_CSEL_3 {TYPE_RW, 111, 1}
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#define SCR_SF_ANA_SF_CFG_AMUX_ACMP4_CH6P_CSEL_3 {TYPE_RW, 112, 1}
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#define SCR_SF_AHB2APB1_COR_IRQ_EN {TYPE_RW, 128, 1}
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#define SCR_SF_AHB2APB1_UNCOR_IRQ_EN {TYPE_RW, 129, 1}
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#define SCR_SF_AHB2APB1_COR_IRQ_CLR {TYPE_RW, 130, 1}
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#define SCR_SF_AHB2APB1_UNCOR_IRQ_CLR {TYPE_RW, 131, 1}
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#define SCR_SF_AHB2APB2_COR_IRQ_EN {TYPE_RW, 132, 1}
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#define SCR_SF_AHB2APB2_UNCOR_IRQ_EN {TYPE_RW, 133, 1}
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#define SCR_SF_AHB2APB2_COR_IRQ_CLR {TYPE_RW, 134, 1}
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#define SCR_SF_AHB2APB2_UNCOR_IRQ_CLR {TYPE_RW, 135, 1}
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#define SCR_SF_AHB2APB3_COR_IRQ_EN {TYPE_RW, 136, 1}
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#define SCR_SF_AHB2APB3_UNCOR_IRQ_EN {TYPE_RW, 137, 1}
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#define SCR_SF_AHB2APB3_COR_IRQ_CLR {TYPE_RW, 138, 1}
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#define SCR_SF_AHB2APB3_UNCOR_IRQ_CLR {TYPE_RW, 139, 1}
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#define SCR_SF_AHB2APB4_COR_IRQ_EN {TYPE_RW, 140, 1}
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#define SCR_SF_AHB2APB4_UNCOR_IRQ_EN {TYPE_RW, 141, 1}
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#define SCR_SF_AHB2APB4_COR_IRQ_CLR {TYPE_RW, 142, 1}
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#define SCR_SF_AHB2APB4_UNCOR_IRQ_CLR {TYPE_RW, 143, 1}
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#define SCR_SF_APB_APBMUX1_MST_DST_IRQ_ENB {TYPE_RW, 160, 1}
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#define SCR_SF_APB_APBMUX1_MST_DST_UNCERR_CLR {TYPE_RW, 161, 1}
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#define SCR_SF_APB_APBMUX1_SLV_SRC_IRQ_ENB {TYPE_RW, 162, 1}
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#define SCR_SF_APB_APBMUX1_SLV_SRC_UNCERR_CLR {TYPE_RW, 163, 1}
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#define SCR_SF_AAPB_MAC_SRC_IRQ_ENB {TYPE_RW, 164, 1}
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#define SCR_SF_AAPB_MAC_SRC_UNCERR_CLR {TYPE_RW, 165, 1}
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#define SCR_SF_AAPB_MAC_DST_IRQ_ENB {TYPE_RW, 166, 1}
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#define SCR_SF_AAPB_MAC_DST_UNCERR_CLR {TYPE_RW, 167, 1}
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#define SCR_SF_APB_DCDC1_MST_DST_IRQ_ENB {TYPE_RW, 172, 1}
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#define SCR_SF_APB_DCDC1_MST_DST_UNCERR_CLR {TYPE_RW, 173, 1}
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#define SCR_SF_APB_DCDC1_SLV_SRC_IRQ_ENB {TYPE_RW, 174, 1}
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#define SCR_SF_APB_DCDC1_SLV_SRC_UNCERR_CLR {TYPE_RW, 175, 1}
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#define SCR_SF_APB_SEC_STORAGE1_MST_DST_IRQ_ENB {TYPE_RW, 176, 1}
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#define SCR_SF_APB_SEC_STORAGE1_MST_DST_UNCERR_CLR {TYPE_RW, 177, 1}
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#define SCR_SF_APB_SEC_STORAGE1_SLV_SRC_IRQ_ENB {TYPE_RW, 178, 1}
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#define SCR_SF_APB_SEC_STORAGE1_SLV_SRC_UNCERR_CLR {TYPE_RW, 179, 1}
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#define SCR_SF_AAPB_XSPI1A_SRC_IRQ_ENB {TYPE_RW, 192, 1}
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#define SCR_SF_AAPB_XSPI1A_SRC_UNCERR_CLR {TYPE_RW, 193, 1}
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#define SCR_SF_AAPB_XSPI1A_DST_IRQ_ENB {TYPE_RW, 194, 1}
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#define SCR_SF_AAPB_XSPI1A_DST_UNCERR_CLR {TYPE_RW, 195, 1}
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#define SCR_SF_AAPB_XSPI1B_SRC_IRQ_ENB {TYPE_RW, 196, 1}
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#define SCR_SF_AAPB_XSPI1B_SRC_UNCERR_CLR {TYPE_RW, 197, 1}
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#define SCR_SF_AAPB_XSPI1B_DST_IRQ_ENB {TYPE_RW, 198, 1}
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#define SCR_SF_AAPB_XSPI1B_DST_UNCERR_CLR {TYPE_RW, 199, 1}
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#define SCR_SF_AAPB_MPC_SEIP_SRC_UNCERR_CLR {TYPE_RW, 209, 1}
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#define SCR_SF_AAPB_MPC_SEIP_DST_UNCERR_CLR {TYPE_RW, 211, 1}
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#define SCR_SF_APB_PMUX3_DEC_SLV_SRC_IRQ_ENB {TYPE_RW, 212, 1}
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#define SCR_SF_APB_PMUX3_DEC_SLV_SRC_UNCERR_CLR {TYPE_RW, 213, 1}
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#define SCR_SF_APB_PMUX3_DEC_MST_DST_IRQ_ENB {TYPE_RW, 214, 1}
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#define SCR_SF_APB_PMUX3_DEC_MST_DST_UNCERR_CLR {TYPE_RW, 215, 1}
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#define SCR_SF_AAPB_APBMUX3_SRC_IRQ_ENB {TYPE_RW, 216, 1}
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#define SCR_SF_AAPB_APBMUX3_SRC_UNCERR_CLR {TYPE_RW, 217, 1}
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#define SCR_SF_AAPB_APBMUX3_DST_IRQ_ENB {TYPE_RW, 218, 1}
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#define SCR_SF_AAPB_APBMUX3_DST_UNCERR_CLR {TYPE_RW, 219, 1}
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#define SCR_SF_APB_APBMUX4_SLV_SRC_IRQ_ENB {TYPE_RW, 220, 1}
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#define SCR_SF_APB_APBMUX4_SLV_SRC_UNCERR_CLR {TYPE_RW, 221, 1}
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#define SCR_SF_APB_APBMUX4_MST_DST_IRQ_ENB {TYPE_RW, 222, 1}
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#define SCR_SF_APB_APBMUX4_MST_DST_UNCERR_CLR {TYPE_RW, 223, 1}
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#define SCR_SF_MPC_XSPI1A_SRC_IRQ_ENB {TYPE_RW, 224, 1}
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#define SCR_SF_MPC_XSPI1A_SRC_UNCERR_CLR {TYPE_RW, 225, 1}
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#define SCR_SF_MPC_XSPI1A_DST_IRQ_ENB {TYPE_RW, 226, 1}
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#define SCR_SF_MPC_XSPI1A_DST_UNCERR_CLR {TYPE_RW, 227, 1}
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#define SCR_SF_MPC_XSPI1B_SRC_IRQ_ENB {TYPE_RW, 228, 1}
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#define SCR_SF_MPC_XSPI1B_SRC_UNCERR_CLR {TYPE_RW, 229, 1}
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#define SCR_SF_MPC_XSPI1B_DST_IRQ_ENB {TYPE_RW, 230, 1}
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#define SCR_SF_MPC_XSPI1B_DST_UNCERR_CLR {TYPE_RW, 231, 1}
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#define SCR_SF_MPC_CR5_SF_SRC_IRQ_ENB {TYPE_RW, 256, 1}
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#define SCR_SF_MPC_CR5_SF_SRC_UNCERR_CLR {TYPE_RW, 257, 1}
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#define SCR_SF_MPC_CR5_SF_DST_IRQ_ENB {TYPE_RW, 258, 1}
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#define SCR_SF_MPC_CR5_SF_DST_UNCERR_CLR {TYPE_RW, 259, 1}
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#define SCR_SF_ANA_SF_CFG_VREF1_VTRIM_4_0 {TYPE_RW, 288, 5}
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#define SCR_SF_SCR_VREF1_PDREF {TYPE_RW, 293, 1}
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#define SCR_SF_ANA_SF_CFG_VREF2_VTRIM_4_0 {TYPE_RW, 294, 5}
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#define SCR_SF_SCR_VREF2_PDREF {TYPE_RW, 299, 1}
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#define SCR_SF_SCAN_SAFMUX_BGR_ANA_SF1_D0_10_8 {TYPE_RW, 320, 3}
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#define SCR_SF_SCAN_SAFMUX_BGR_ANA_SF1_D0_7_0 {TYPE_RW, 323, 8}
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#define SCR_SF_SCR_BGR_ANA_SF1_TRIM_SEL {TYPE_RW, 331, 1}
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#define SCR_SF_SCAN_SAFMUX_BGR_ANA_SF2_D0_10_8 {TYPE_RW, 352, 3}
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#define SCR_SF_SCAN_SAFMUX_BGR_ANA_SF2_D0_7_0 {TYPE_RW, 355, 8}
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#define SCR_SF_SCR_BGR_ANA_SF2_TRIM_SEL {TYPE_RW, 363, 1}
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#define SCR_SF_SCAN_SAFMUX_BGR_SF_D0_10_8 {TYPE_RW, 384, 3}
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#define SCR_SF_SCAN_SAFMUX_BGR_SF_D0_7_0 {TYPE_RW, 387, 8}
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#define SCR_SF_BGR33_SF_SCR_BGR33_SF_TRIM_SEL {TYPE_RW, 395, 1}
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#define SCR_SF_SCR_XSPI1_PA_SS1_SCLKB_SEL {TYPE_RW, 416, 1}
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#define SCR_SF_SCR_XSPI1_PB_SS1_SCLKB_SEL {TYPE_RW, 417, 1}
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#define SCR_SF_SCR_CR5_SF_CPUHALT0 {TYPE_RW, 448, 1}
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#define SCR_SF_SCR_CR5_SF_CPUHALT1 {TYPE_RW, 449, 1}
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#define SCR_SF_CR5_SF_SCR_CR5_IRQ_CLR {TYPE_RW, 450, 1}
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#define SCR_SF_CR5_SF_SCR_CR5_VICADDR_DISABLE {TYPE_RW, 451, 1}
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#define SCR_SF_SCR_CR5_SF_DCCMINP_0 {TYPE_RW, 452, 1}
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#define SCR_SF_ANA_SF_CFG_APD_A_A0_CTRL_3_0 {TYPE_RW, 544, 4}
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#define SCR_SF_ANA_SF_CFG_APD_A_A1_CTRL_3_0 {TYPE_RW, 548, 4}
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#define SCR_SF_ANA_SF_CFG_APD_A_A2_CTRL_3_0 {TYPE_RW, 552, 4}
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#define SCR_SF_ANA_SF_CFG_APD_A_A3_CTRL_3_0 {TYPE_RW, 556, 4}
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#define SCR_SF_ANA_SF_CFG_APD_A_A4_CTRL_3_0 {TYPE_RW, 560, 4}
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#define SCR_SF_ANA_SF_CFG_APD_A_A5_CTRL_3_0 {TYPE_RW, 564, 4}
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#define SCR_SF_ANA_SF_CFG_APD_A_A6_CTRL_3_0 {TYPE_RW, 568, 4}
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#define SCR_SF_ANA_SF_CFG_APD_A_A7_CTRL_3_0 {TYPE_RW, 572, 4}
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#define SCR_SF_ANA_SF_CFG_APD_A_A8_CTRL_3_0 {TYPE_RW, 576, 4}
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#define SCR_SF_ANA_SF_CFG_APD_A_A9_CTRL_3_0 {TYPE_RW, 580, 4}
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#define SCR_SF_ANA_SF_CFG_APD_A_A10_CTRL_3_0 {TYPE_RW, 584, 4}
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#define SCR_SF_ANA_SF_CFG_APD_A_A11_CTRL_3_0 {TYPE_RW, 588, 4}
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#define SCR_SF_ANA_SF_CFG_APD_A_A12_CTRL_3_0 {TYPE_RW, 592, 4}
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#define SCR_SF_ANA_SF_CFG_APD_A_A13_CTRL_3_0 {TYPE_RW, 596, 4}
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#define SCR_SF_ANA_SF_CFG_APD_A_A14_CTRL_3_0 {TYPE_RW, 600, 4}
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#define SCR_SF_ANA_SF_CFG_APD_A_A15_CTRL_3_0 {TYPE_RW, 604, 4}
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#define SCR_SF_ANA_SF_CFG_APD_A_B0_CTRL_3_0 {TYPE_RW, 608, 4}
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#define SCR_SF_ANA_SF_CFG_APD_A_B1_CTRL_3_0 {TYPE_RW, 612, 4}
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#define SCR_SF_ANA_SF_CFG_APD_A_B2_CTRL_3_0 {TYPE_RW, 616, 4}
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#define SCR_SF_ANA_SF_CFG_APD_A_B3_CTRL_3_0 {TYPE_RW, 620, 4}
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#define SCR_SF_ANA_SF_CFG_APD_A_B4_CTRL_3_0 {TYPE_RW, 624, 4}
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#define SCR_SF_ANA_SF_CFG_APD_A_B5_CTRL_3_0 {TYPE_RW, 628, 4}
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#define SCR_SF_ANA_SF_CFG_APD_A_B6_CTRL_3_0 {TYPE_RW, 632, 4}
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#define SCR_SF_ANA_SF_CFG_APD_A_B7_CTRL_3_0 {TYPE_RW, 636, 4}
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#define SCR_SF_ANA_SF_CFG_APD_A_B8_CTRL_3_0 {TYPE_RW, 640, 4}
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#define SCR_SF_ANA_SF_CFG_APD_A_B9_CTRL_3_0 {TYPE_RW, 644, 4}
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#define SCR_SF_ANA_SF_CFG_APD_A_B10_CTRL_3_0 {TYPE_RW, 648, 4}
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#define SCR_SF_ANA_SF_CFG_APD_A_B11_CTRL_3_0 {TYPE_RW, 652, 4}
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#define SCR_SF_ANA_SF_CFG_APD_A_B12_CTRL_3_0 {TYPE_RW, 656, 4}
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#define SCR_SF_ANA_SF_CFG_APD_A_B13_CTRL_3_0 {TYPE_RW, 660, 4}
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#define SCR_SF_ANA_SF_CFG_APD_A_B14_CTRL_3_0 {TYPE_RW, 664, 4}
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#define SCR_SF_ANA_SF_CFG_APD_A_B15_CTRL_3_0 {TYPE_RW, 668, 4}
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#define SCR_SF_ANA_SF_CFG_APD_A_C0_CTRL_3_0 {TYPE_RW, 672, 4}
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#define SCR_SF_ANA_SF_CFG_APD_A_C1_CTRL_3_0 {TYPE_RW, 676, 4}
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#define SCR_SF_ANA_SF_CFG_APD_A_C2_CTRL_3_0 {TYPE_RW, 680, 4}
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#define SCR_SF_ANA_SF_CFG_APD_A_C3_CTRL_3_0 {TYPE_RW, 684, 4}
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#define SCR_SF_ANA_SF_CFG_APD_A_C4_CTRL_3_0 {TYPE_RW, 688, 4}
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#define SCR_SF_ANA_SF_CFG_APD_A_C5_CTRL_3_0 {TYPE_RW, 692, 4}
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#define SCR_SF_ANA_SF_CFG_APD_A_C6_CTRL_3_0 {TYPE_RW, 696, 4}
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#define SCR_SF_ANA_SF_CFG_APD_A_C7_CTRL_3_0 {TYPE_RW, 700, 4}
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#define SCR_SF_ANA_SF_CFG_AMUX_REF_P_CSEL_3_0 {TYPE_RW, 736, 4}
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#define SCR_SF_ANA_SF_CFG_AMUX_REF_N_CSEL_3_0 {TYPE_RW, 740, 4}
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#define SCR_SF_SCR_SF_DEBUG_MODE {TYPE_RW, 768, 1}
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#define SCR_SF_ENET1_SBD_FLOWCTRL_I_4_0 {TYPE_RW, 800, 5}
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#define SCR_SF_SCR_ENET1_CAP_COMP_0_OE {TYPE_RW, 805, 1}
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#define SCR_SF_SCR_ENET1_CAP_COMP_1_OE {TYPE_RW, 806, 1}
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#define SCR_SF_SCR_ENET1_CAP_COMP_2_OE {TYPE_RW, 807, 1}
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#define SCR_SF_SCR_ENET1_CAP_COMP_3_OE {TYPE_RW, 808, 1}
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#define SCR_SF_SCR_ENET1_CLK_RMII_OE {TYPE_RW, 809, 1}
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#define SCR_SF_ETMR1_CMP_A_ZO_EN {TYPE_RW, 832, 1}
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#define SCR_SF_ETMR1_CMP_B_ZO_EN {TYPE_RW, 833, 1}
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#define SCR_SF_ETMR1_CMP_C_ZO_EN {TYPE_RW, 834, 1}
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#define SCR_SF_ETMR1_CMP_D_ZO_EN {TYPE_RW, 835, 1}
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#define SCR_SF_ETMR1_CMP_A_CBC_EN {TYPE_RW, 836, 1}
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#define SCR_SF_ETMR1_CMP_B_CBC_EN {TYPE_RW, 837, 1}
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#define SCR_SF_ETMR1_CMP_C_CBC_EN {TYPE_RW, 838, 1}
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#define SCR_SF_ETMR1_CMP_D_CBC_EN {TYPE_RW, 839, 1}
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#define SCR_SF_ETMR1_CMP_A0_SW_FRC_DIS {TYPE_RW, 840, 1}
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#define SCR_SF_ETMR1_CMP_A1_SW_FRC_DIS {TYPE_RW, 841, 1}
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#define SCR_SF_ETMR1_CMP_B0_SW_FRC_DIS {TYPE_RW, 842, 1}
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#define SCR_SF_ETMR1_CMP_B1_SW_FRC_DIS {TYPE_RW, 843, 1}
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#define SCR_SF_ETMR1_CMP_C0_SW_FRC_DIS {TYPE_RW, 844, 1}
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#define SCR_SF_ETMR1_CMP_C1_SW_FRC_DIS {TYPE_RW, 845, 1}
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#define SCR_SF_ETMR1_CMP_D0_SW_FRC_DIS {TYPE_RW, 846, 1}
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#define SCR_SF_ETMR1_CMP_D1_SW_FRC_DIS {TYPE_RW, 847, 1}
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#define SCR_SF_ETMR2_CMP_A_ZO_EN {TYPE_RW, 848, 1}
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#define SCR_SF_ETMR2_CMP_B_ZO_EN {TYPE_RW, 849, 1}
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#define SCR_SF_ETMR2_CMP_C_ZO_EN {TYPE_RW, 850, 1}
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#define SCR_SF_ETMR2_CMP_D_ZO_EN {TYPE_RW, 851, 1}
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#define SCR_SF_ETMR2_CMP_A_CBC_EN {TYPE_RW, 852, 1}
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#define SCR_SF_ETMR2_CMP_B_CBC_EN {TYPE_RW, 853, 1}
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#define SCR_SF_ETMR2_CMP_C_CBC_EN {TYPE_RW, 854, 1}
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#define SCR_SF_ETMR2_CMP_D_CBC_EN {TYPE_RW, 855, 1}
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#define SCR_SF_ETMR2_CMP_A0_SW_FRC_DIS {TYPE_RW, 856, 1}
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#define SCR_SF_ETMR2_CMP_A1_SW_FRC_DIS {TYPE_RW, 857, 1}
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#define SCR_SF_ETMR2_CMP_B0_SW_FRC_DIS {TYPE_RW, 858, 1}
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#define SCR_SF_ETMR2_CMP_B1_SW_FRC_DIS {TYPE_RW, 859, 1}
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#define SCR_SF_ETMR2_CMP_C0_SW_FRC_DIS {TYPE_RW, 860, 1}
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#define SCR_SF_ETMR2_CMP_C1_SW_FRC_DIS {TYPE_RW, 861, 1}
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#define SCR_SF_ETMR2_CMP_D0_SW_FRC_DIS {TYPE_RW, 862, 1}
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#define SCR_SF_ETMR2_CMP_D1_SW_FRC_DIS {TYPE_RW, 863, 1}
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#define SCR_SF_EPWM1_CMP_A_ZO_EN {TYPE_RW, 864, 1}
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#define SCR_SF_EPWM1_CMP_B_ZO_EN {TYPE_RW, 865, 1}
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#define SCR_SF_EPWM1_CMP_C_ZO_EN {TYPE_RW, 866, 1}
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#define SCR_SF_EPWM1_CMP_D_ZO_EN {TYPE_RW, 867, 1}
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#define SCR_SF_EPWM1_CMP_A_CBC_EN {TYPE_RW, 868, 1}
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#define SCR_SF_EPWM1_CMP_B_CBC_EN {TYPE_RW, 869, 1}
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#define SCR_SF_EPWM1_CMP_C_CBC_EN {TYPE_RW, 870, 1}
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#define SCR_SF_EPWM1_CMP_D_CBC_EN {TYPE_RW, 871, 1}
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#define SCR_SF_EPWM1_CMP_A0_SW_FRC_DIS {TYPE_RW, 872, 1}
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#define SCR_SF_EPWM1_CMP_A1_SW_FRC_DIS {TYPE_RW, 873, 1}
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#define SCR_SF_EPWM1_CMP_B0_SW_FRC_DIS {TYPE_RW, 874, 1}
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#define SCR_SF_EPWM1_CMP_B1_SW_FRC_DIS {TYPE_RW, 875, 1}
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#define SCR_SF_EPWM1_CMP_C0_SW_FRC_DIS {TYPE_RW, 876, 1}
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#define SCR_SF_EPWM1_CMP_C1_SW_FRC_DIS {TYPE_RW, 877, 1}
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#define SCR_SF_EPWM1_CMP_D0_SW_FRC_DIS {TYPE_RW, 878, 1}
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#define SCR_SF_EPWM1_CMP_D1_SW_FRC_DIS {TYPE_RW, 879, 1}
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#define SCR_SF_EPWM2_CMP_A_ZO_EN {TYPE_RW, 880, 1}
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#define SCR_SF_EPWM2_CMP_B_ZO_EN {TYPE_RW, 881, 1}
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#define SCR_SF_EPWM2_CMP_C_ZO_EN {TYPE_RW, 882, 1}
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#define SCR_SF_EPWM2_CMP_D_ZO_EN {TYPE_RW, 883, 1}
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#define SCR_SF_EPWM2_CMP_A_CBC_EN {TYPE_RW, 884, 1}
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#define SCR_SF_EPWM2_CMP_B_CBC_EN {TYPE_RW, 885, 1}
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#define SCR_SF_EPWM2_CMP_C_CBC_EN {TYPE_RW, 886, 1}
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#define SCR_SF_EPWM2_CMP_D_CBC_EN {TYPE_RW, 887, 1}
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#define SCR_SF_EPWM2_CMP_A0_SW_FRC_DIS {TYPE_RW, 888, 1}
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#define SCR_SF_EPWM2_CMP_A1_SW_FRC_DIS {TYPE_RW, 889, 1}
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#define SCR_SF_EPWM2_CMP_B0_SW_FRC_DIS {TYPE_RW, 890, 1}
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#define SCR_SF_EPWM2_CMP_B1_SW_FRC_DIS {TYPE_RW, 891, 1}
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#define SCR_SF_EPWM2_CMP_C0_SW_FRC_DIS {TYPE_RW, 892, 1}
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#define SCR_SF_EPWM2_CMP_C1_SW_FRC_DIS {TYPE_RW, 893, 1}
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#define SCR_SF_EPWM2_CMP_D0_SW_FRC_DIS {TYPE_RW, 894, 1}
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#define SCR_SF_EPWM2_CMP_D1_SW_FRC_DIS {TYPE_RW, 895, 1}
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#define SCR_SF_ETMR1_MUX_CPT_EN {TYPE_RW, 896, 1}
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#define SCR_SF_ETMR2_MUX_CPT_EN {TYPE_RW, 897, 1}
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#define SCR_SF_SCR_SF_EMA_UPD {TYPE_RW, 1088, 1}
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#define SCR_SF_SCR_AP_EMA_UPD {TYPE_RW, 1120, 1}
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#define SCR_SF_AAPB_PLL1_SRC_IRQ_ENB {TYPE_RW, 1152, 1}
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#define SCR_SF_AAPB_PLL1_SRC_UNCERR_CLR {TYPE_RW, 1153, 1}
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#define SCR_SF_AAPB_PLL1_DST_IRQ_ENB {TYPE_RW, 1154, 1}
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#define SCR_SF_AAPB_PLL1_DST_UNCERR_CLR {TYPE_RW, 1155, 1}
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#define SCR_SF_AAPB_PLL2_SRC_IRQ_ENB {TYPE_RW, 1156, 1}
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#define SCR_SF_AAPB_PLL2_SRC_UNCERR_CLR {TYPE_RW, 1157, 1}
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#define SCR_SF_AAPB_PLL2_DST_IRQ_ENB {TYPE_RW, 1158, 1}
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#define SCR_SF_AAPB_PLL2_DST_UNCERR_CLR {TYPE_RW, 1159, 1}
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#define SCR_SF_AAPB_PLL3_SRC_IRQ_ENB {TYPE_RW, 1160, 1}
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#define SCR_SF_AAPB_PLL3_SRC_UNCERR_CLR {TYPE_RW, 1161, 1}
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#define SCR_SF_AAPB_PLL3_DST_IRQ_ENB {TYPE_RW, 1162, 1}
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#define SCR_SF_AAPB_PLL3_DST_UNCERR_CLR {TYPE_RW, 1163, 1}
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#define SCR_SF_USB_I_USB2_WAKE_USER {TYPE_RW, 1184, 1}
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#define SCR_SF_IROMC_LP_MEM_STICKY_STICKY_SET {TYPE_RW, 1216, 1}
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#define SCR_SF_MEMCTRL_OVRD_EN {TYPE_RW, 1280, 1}
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#define SCR_SF_URFSPHD_EMA_2_0 {TYPE_RW, 1312, 3}
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#define SCR_SF_URFSPHD_EMAW_1_0 {TYPE_RW, 1315, 2}
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#define SCR_SF_URFSPHD_EMAS {TYPE_RW, 1317, 1}
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#define SCR_SF_URFSPHD_WABL {TYPE_RW, 1318, 1}
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#define SCR_SF_URFSPHD_WABLM_1_0 {TYPE_RW, 1319, 2}
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#define SCR_SF_URFSPHD_RAWL {TYPE_RW, 1321, 1}
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#define SCR_SF_URFSPHD_RAWLM_1_0 {TYPE_RW, 1322, 2}
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#define SCR_SF_GSRSPUHD_EMA_2_0 {TYPE_RW, 1324, 3}
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#define SCR_SF_GSRSPUHD_EMAW_1_0 {TYPE_RW, 1327, 2}
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#define SCR_SF_GSRSPUHD_EMAS {TYPE_RW, 1329, 1}
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#define SCR_SF_GSRSPUHD_WABL {TYPE_RW, 1330, 1}
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#define SCR_SF_GSRSPUHD_WABLM_1_0 {TYPE_RW, 1331, 2}
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#define SCR_SF_GSRSPUHD_RAWL {TYPE_RW, 1333, 1}
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#define SCR_SF_GSRSPUHD_RAWLM_1_0 {TYPE_RW, 1334, 2}
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#define SCR_SF_GSRSPHD_EMA_2_0 {TYPE_RW, 1336, 3}
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#define SCR_SF_GSRSPHD_EMAW_1_0 {TYPE_RW, 1339, 2}
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#define SCR_SF_GSRSPHD_EMAS {TYPE_RW, 1341, 1}
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#define SCR_SF_GSRSPHD_WABL {TYPE_RW, 1342, 1}
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#define SCR_SF_GSRSPHD_WABLM_0 {TYPE_RW, 1343, 1}
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#define SCR_SF_GSRSPHD_WABLM_1 {TYPE_RW, 1344, 1}
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#define SCR_SF_GSRSPHD_RAWL {TYPE_RW, 1345, 1}
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#define SCR_SF_GSRSPHD_RAWLM_1_0 {TYPE_RW, 1346, 2}
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#define SCR_SF_USRSPHD_EMA_2_0 {TYPE_RW, 1348, 3}
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#define SCR_SF_USRSPHD_EMAW_1_0 {TYPE_RW, 1351, 2}
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#define SCR_SF_USRSPHD_EMAS {TYPE_RW, 1353, 1}
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#define SCR_SF_USRSPHD_WABL {TYPE_RW, 1354, 1}
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#define SCR_SF_USRSPHD_WABLM_2_0 {TYPE_RW, 1355, 3}
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#define SCR_SF_USRSPHD_RAWL {TYPE_RW, 1358, 1}
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#define SCR_SF_USRSPHD_RAWLM_1_0 {TYPE_RW, 1359, 2}
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#define SCR_SF_GRFSPHD_EMA_2_0 {TYPE_RW, 1361, 3}
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#define SCR_SF_GRFSPHD_EMAW_1_0 {TYPE_RW, 1364, 2}
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#define SCR_SF_GRFSPHD_EMAS {TYPE_RW, 1366, 1}
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#define SCR_SF_GRFSPHD_WABL {TYPE_RW, 1367, 1}
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#define SCR_SF_GRFSPHD_WABLM_1_0 {TYPE_RW, 1368, 2}
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#define SCR_SF_GRFSPHD_RAWL {TYPE_RW, 1370, 1}
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#define SCR_SF_GRFSPHD_RAWLM_1_0 {TYPE_RW, 1371, 2}
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#define SCR_SF_GRF2PHD_EMAA_2_0 {TYPE_RW, 1373, 3}
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#define SCR_SF_GRF2PHD_EMAB_2_0 {TYPE_RW, 1376, 3}
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#define SCR_SF_GRF2PHD_EMASA {TYPE_RW, 1379, 1}
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#define SCR_SF_ROM_EMA_2_0 {TYPE_RW, 1380, 3}
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#define SCR_SF_ROM_KEN {TYPE_RW, 1383, 1}
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#define SCR_SF_BTI_SF_M0_TIMEOUT_DIV_7_0 {TYPE_R16W16, 0, 8}
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#define SCR_SF_BTI_SF_M0_BTI_EN {TYPE_R16W16, 8, 1}
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#define SCR_SF_BTI_SF_M0_UNCOR_IRQ_EN {TYPE_R16W16, 9, 1}
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#define SCR_SF_BTI_SF_M0_UNCOR_IRQ_CLR {TYPE_R16W16, 10, 1}
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#define SCR_SF_BTI_SF_P0_TIMEOUT_DIV_7_0 {TYPE_R16W16, 32, 8}
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#define SCR_SF_BTI_SF_P0_BTI_EN {TYPE_R16W16, 40, 1}
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#define SCR_SF_BTI_SF_P0_UNCOR_IRQ_EN {TYPE_R16W16, 41, 1}
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#define SCR_SF_BTI_SF_P0_UNCOR_IRQ_CLR {TYPE_R16W16, 42, 1}
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#define SCR_SF_BTI_SF_AHB_TIMEOUT_DIV_7_0 {TYPE_R16W16, 64, 8}
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#define SCR_SF_BTI_SF_AHB_BTI_EN {TYPE_R16W16, 72, 1}
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#define SCR_SF_BTI_SF_AHB_UNCOR_IRQ_EN {TYPE_R16W16, 73, 1}
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#define SCR_SF_BTI_SF_AHB_UNCOR_IRQ_CLR {TYPE_R16W16, 74, 1}
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#define SCR_SF_CANFD16_CANFD_DEBOUNCE_TIME_3_0 {TYPE_R16W16, 480, 4}
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#define SCR_SF_CANFD16_STOP_DOZE_SEL {TYPE_R16W16, 484, 1}
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#define SCR_SF_CANFD21_CANFD_DEBOUNCE_TIME_3_0 {TYPE_R16W16, 512, 4}
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#define SCR_SF_CANFD21_STOP_DOZE_SEL {TYPE_R16W16, 516, 1}
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#define SCR_SF_CANFD3_CANFD_DEBOUNCE_TIME_3_0 {TYPE_R16W16, 544, 4}
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#define SCR_SF_CANFD3_STOP_DOZE_SEL {TYPE_R16W16, 548, 1}
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#define SCR_SF_CANFD4_CANFD_DEBOUNCE_TIME_3_0 {TYPE_R16W16, 549, 4}
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#define SCR_SF_CANFD4_STOP_DOZE_SEL {TYPE_R16W16, 553, 1}
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#define SCR_SF_CANFD5_CANFD_DEBOUNCE_TIME_3_0 {TYPE_R16W16, 576, 4}
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#define SCR_SF_CANFD5_STOP_DOZE_SEL {TYPE_R16W16, 580, 1}
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#define SCR_SF_CANFD6_CANFD_DEBOUNCE_TIME_3_0 {TYPE_R16W16, 581, 4}
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#define SCR_SF_CANFD6_STOP_DOZE_SEL {TYPE_R16W16, 585, 1}
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#define SCR_SF_CANFD7_CANFD_DEBOUNCE_TIME_3_0 {TYPE_R16W16, 608, 4}
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#define SCR_SF_CANFD7_STOP_DOZE_SEL {TYPE_R16W16, 612, 1}
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#define SCR_SF_CANFD23_CANFD_DEBOUNCE_TIME_3_0 {TYPE_R16W16, 613, 4}
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#define SCR_SF_CANFD23_STOP_DOZE_SEL {TYPE_R16W16, 617, 1}
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#define SCR_SF_BTI_SF_M0_CHN_IDLE {TYPE_R16W16, 16, 1}
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#define SCR_SF_BTI_SF_P0_CHN_IDLE {TYPE_R16W16, 48, 1}
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#define SCR_SF_BTI_SF_AHB_CHN_IDLE {TYPE_R16W16, 80, 1}
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#endif /*_SCR_HW_H_*/ |