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liumin
2025-12-06 18:46:56 +08:00
parent 7035f73327
commit d17afb4e84
2106 changed files with 1455022 additions and 14 deletions
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56
boards/e3_176_ref/app_demo/eth-xip/sf/configs/clock_cfg.c Normal file
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#include <sdrv_ckgen.h>
#include <clock_ip.h>
#include <part.h>
#if ((CONFIG_E3210) || (CONFIG_E3110))
const sdrv_ckgen_rate_config_t g_ip_config = {
.config_num = 7,
.config_nodes[0].clk_node = CLK_NODE(g_ckgen_ip_uart_sf_1_to_8),
.config_nodes[0].rate = 83000000,
.config_nodes[1].clk_node = CLK_NODE(g_ckgen_ip_enet1_tx),
.config_nodes[1].rate = 250000000,
.config_nodes[2].clk_node = CLK_NODE(g_ckgen_ip_enet1_rmii),
.config_nodes[2].rate = 50000000,
.config_nodes[3].clk_node = CLK_NODE(g_ckgen_ip_enet1_phy_ref),
.config_nodes[3].rate = 125000000,
.config_nodes[4].clk_node = CLK_NODE(g_ckgen_ip_enet1_timer_sec),
.config_nodes[4].rate = 125000000,
.config_nodes[5].clk_node = CLK_NODE(g_ckgen_ip_can),
.config_nodes[5].rate = 40000000,
.config_nodes[6].clk_node = CLK_NODE(g_ckgen_ip_uart_sf_7_to_12),
.config_nodes[6].rate = 83000000,
};
#else
const sdrv_ckgen_rate_config_t g_ip_config = {
.config_num = 7,
.config_nodes[0].clk_node = CLK_NODE(g_ckgen_ip_uart_sf_1_to_6),
.config_nodes[0].rate = 83000000,
.config_nodes[1].clk_node = CLK_NODE(g_ckgen_ip_enet1_tx),
.config_nodes[1].rate = 250000000,
.config_nodes[2].clk_node = CLK_NODE(g_ckgen_ip_enet1_rmii),
.config_nodes[2].rate = 50000000,
.config_nodes[3].clk_node = CLK_NODE(g_ckgen_ip_enet1_phy_ref),
.config_nodes[3].rate = 125000000,
.config_nodes[4].clk_node = CLK_NODE(g_ckgen_ip_enet1_timer_sec),
.config_nodes[4].rate = 125000000,
.config_nodes[5].clk_node = CLK_NODE(g_ckgen_ip_can),
.config_nodes[5].rate = 40000000,
.config_nodes[6].clk_node = CLK_NODE(g_ckgen_ip_uart_sf_7_to_12),
.config_nodes[6].rate = 83000000,
};
#endif
const sdrv_ckgen_config_t g_clock_config = {
#if CONFIG_XIP_MODE
.pre_bus_config = NULL,
.pll_config = NULL,
.bus_config = NULL,
#else
.pre_bus_config = &g_pre_bus_config,
.pll_config = &g_pll_config,
.bus_config = &g_bus_config,
#endif
.core_config = NULL,
.ip_config = &g_ip_config,
.gating_config = NULL,
};

9
boards/e3_176_ref/app_demo/eth-xip/sf/configs/clock_cfg.h Normal file
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#ifndef SDRV_CLOCK_CFG_H_
#define SDRV_CLOCK_CFG_H_
#include <sdrv_ckgen.h>
#include <clock_ip.h>
extern sdrv_ckgen_config_t g_clock_config;
#endif /* SDRV_CLOCK_CFG_H_ */

173
boards/e3_176_ref/app_demo/eth-xip/sf/configs/config.h Normal file
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/**
* @file config.h
* @brief SSDK configuration header file.
*
* @copyright Copyright (c) 2022 Semidrive Semiconductor.
* All rights reserved.
*/
/**
* @brief Enable ARM I-Cache and D-Cache operations.
*
* If CONFIG_ARCH_WITH_CACHE is defined, ARM I-Cache and D-Cache
* operations are enabled and you can call functions defiend in cache.h to
* manage caches.
*/
#define CONFIG_ARCH_WITH_CACHE 1
/**
* @brief ARM cache line size in bytes.
*
* Cortex R5 cache line length is 8 words (256 bits).
*/
#define CONFIG_ARCH_CACHE_LINE 32
/**
* @brief Enable I-Cache on power up.
*
* If CONFIG_ARCH_EARLY_ENABLE_ICACHE is defined, ARM I-Cache is
* enabled on power up.
*/
#define CONFIG_ARCH_EARLY_ENABLE_ICACHE 1
/**
* @brief Enable D-Cache on power up.
*
* If CONFIG_ARCH_EARLY_ENABLE_DCACHE is defined, ARM D-Cache is enabled on
* power up.
*/
#define CONFIG_ARCH_EARLY_ENABLE_DCACHE 1
/**
* @brief Enable ARM FPU.
*
* If CONFIG_ARCH_WITH_FPU is defined, ARM floating processing unit (FPU) is
* enabled.
*/
#define CONFIG_ARCH_WITH_FPU 1
/**
* @brief SemiDrive E3 product macro.
*/
#define CONFIG_ARCH_CHIP_E3 1
/**
* @brief Enable ARM TCM.
*
* If CONFIG_ARCH_WITH_TCM is defined, ARM tightly coupled memory
* (TCM) driver is enabed.
*/
#define CONFIG_ARM_WITH_TCM 1
/**
* @brief Enable ARM CP 15 operations.
*
* If CONFIG_ARCH_WITH_CP15 is defined, ARM CP15 coprocessor
* instructions are used.
*/
#define CONFIG_ARM_WITH_CP15 1
/**
* @brief Enable ARM PMU operations.
*
* If CONFIG_ARCH_WITH_PMU is defined, ARM performance monitor
* unit (PMU) functions can be used to manage PMU.
*/
#define CONFIG_ARM_WITH_PMU 1
/**
* @brief Enable Cortex R5 TCM A area.
*/
#define CONFIG_ARMV7R_USE_TCMA 1
/**
* @brief Cortex R5 TCM A base address.
*
* TCM A base address is configured on power up, by setting CP15. Note that
* this address could be different from TCMx_BASE address defined in
* regs_base.h, which is the bus address used by other AXI masters to access
* TCMA from outside the Cortex R5 core.
*/
#define CONFIG_ARMV7R_TCMA_BASE 0x10000
/**
* @brief Enable Cortex R5 TCM B area.
*/
#define CONFIG_ARMV7R_USE_TCMB 1
/**
* @brief Cortex R5 TCM B base address.
*
* TCM B base address is configured on power up, by setting CP15. Note that
* this address could be different from TCMx_BASE address defined in
* regs_base.h, which is the bus address used by other AXI masters to access
* TCMB from outside the Cortex R5 core.
*/
#define CONFIG_ARMV7R_TCMB_BASE 0x0
/**
* @brief Enable VIC driver
*/
#define CONFIG_IRQ 1
/**
* @brief Enable vectored IRQ mode.
*
* In vectored IRQ mode if IRQ signal received, R5 acknowledge to
* VIC through dedicated hardware channel and get interrupt address
* from VIC directly.
*
* If not configured, interupt address is always 0x18, and interrupt routing
* will read VICADDRESS register to acknowledge to VIC and get interrupt
* nubmer, and branch to user ISR.
*/
#define CONFIG_VIC_IRQ_INTERRUPT_MODE 1
/**
* @brief Enable Ethernet controller driver, and LWIP stacks.
*/
#define CONFIG_ETH 1
/**
* @brief Enable debug logs and asserts.
*
* Define CONFIG_DEBUG if you want ssdk_printf() logs, as well as PANIC()
* and ASSERT() dumps.
*/
#define CONFIG_DEBUG 1
/**
* @brief SSDK Log level.
*
* ssdk_printf() logs with "level" no greater than CONFIG_DEBUG_LEVEL are
* shown, while other logs are ignored. See log levels defined in debug.h.
*/
#define CONFIG_DEBUG_LEVEL SSDK_NOTICE
/**
* @brief Enable printf function.
*
* The middleware/printf library provides simple printf function.
* CONFIG_PRINTF_LIB is valid only when CONFIG_DEBUG is defined.
*/
#define CONFIG_PRINTF_LIB 1
/**
* @brief Enable early memory section copy on power up.
*
* If CONFIG_EARLYCOY is defined, the system will copy memory sections
* from their load address to link address on power up. This is required for
* GCC generated images when there are memory sections which have
* different load address (LMA) and running address (VMA). IAR automatically
* perform initial memory recocations so CONFIG_EARLYCOPY is not required
* for IAR.
*/
#define CONFIG_EARLYCOPY 1
/**
* @brief Enable XIP mode
*
* If CONFIG_XIP_MODE is defined, the system will running in flash (via XSPI1 controler).
* When running in XIP mode, we cannot initialize PLL1 and XSPI1 modulue
*/
#define CONFIG_XIP_MODE 1

79
boards/e3_176_ref/app_demo/eth-xip/sf/configs/eth_cfg.c Normal file
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#if CONFIG_ETH
#include <stdbool.h>
#include "reg.h"
#include "regs_base.h"
#include "irq_num.h"
#include "scr_hw.h"
#include "sdrv_scr.h"
#include "scr_cfg.h"
#include "sdrv_pinctrl.h"
#include "sdrv_gpio.h"
#include "sdrv_eth.h"
#include <lwip/init.h>
#include <part.h>
#define PHY_INTF_SEL 0x2080
struct net_driver_s g_eth1_dev;
static void set_phyif_mode(uint32_t base, eth_phy_intf_mode_type mode)
{
uint32_t v;
/* Config MII interface. */
if (mode == ETH_PHY_INTF_SEL_MII)
v = 0;
else if (mode == ETH_PHY_INTF_SEL_RMII) {
if (base == APB_ENET1_BASE) {
const scr_signal_t rmii_oe = SCR_SF_SCR_ENET1_CLK_RMII_OE;
scr_set(&g_scr_ctrl, &rmii_oe, 1);
}
#if ((CONFIG_E3210) || (CONFIG_E3110))
else {
const scr_signal_t rmii_oe = SCR_SF_SCR_ENET2_CLK_RMII_OE;
scr_set(&g_scr_ctrl, &rmii_oe, 1);
}
#endif
v = 4;
}
else
v = 1;
writel(v, base + PHY_INTF_SEL);
}
static phy_dev_t g_phy_arr1[] = {
{
.phy_addr = 0,//20240721 <20>޸<EFBFBD>
.duplex_mode = ETH_PHY_DUPLEX_MODE_FULL,
.speed = PHY_SPEED_100,
.auto_negotiation = true//20240721 <20>޸<EFBFBD>
},
/* Invalid phy dev to indicate end of array. */
{
.phy_addr = ~0,
}
};
static dwc_eth_config_t g_eth1_cfg = {
.base = APB_ENET1_BASE,
.irq_num = ENET1_SBD_INTR_NUM,
.mtu = 1500,
.dma_bus_width = 64,
.phy_intf_mode = ETH_PHY_INTF_SEL_RMII,
.set_phy_intf = set_phyif_mode,
.ip = {192, 168, 17, 20},
.mask = {255, 255, 255, 0},
.phy = g_phy_arr1
};
void board_eth_init(void)
{
dwc_eth_probe(&g_eth1_dev, &g_eth1_cfg);
lwip_init();
}
#endif

12
boards/e3_176_ref/app_demo/eth-xip/sf/configs/eth_cfg.h Normal file
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#ifndef _ETH_CFG_H_
#define _ETH_CFG_H_
#if CONFIG_ETH
extern struct net_driver_s g_eth1_dev;
void board_eth_init(void);
#endif
#endif

315
boards/e3_176_ref/app_demo/eth-xip/sf/configs/flexcan_cfg.c Normal file
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#include <flexcan_cfg.h>
#include <sdrv_flexcan.h>
#include "interface_config.h"
#include "app/app_differential_drive.h"
const flexcan_config_t g_flexcan_config = {
.clkSrc = FLEXCAN_ClkSrcPeri, /* 40MHz */
.maxMbNum = 64U,
.enableSelfWakeup = true,
.enableIndividMask = true,
.enableCANFD = false,
BAUDRATE_1M_5M,
.enableLBUFTransmittedFirst = true
};
const flexcan_config_t can_0_config = {
.clkSrc = FLEXCAN_ClkSrcPeri, /* 40MHz */
.maxMbNum = 64U,
.enableSelfWakeup = true,
.enableIndividMask = true,
.enableCANFD = false,
BAUDRATE_250k,
.enableLBUFTransmittedFirst = true
};
const flexcan_config_t can_1_config = {
.clkSrc = FLEXCAN_ClkSrcPeri, /* 40MHz */
.maxMbNum = 64U,
.enableSelfWakeup = true,
.enableIndividMask = true,
.enableCANFD = false,
BAUDRATE_250k,
.enableLBUFTransmittedFirst = true
};
const flexcan_config_t can_2_config = {
.clkSrc = FLEXCAN_ClkSrcPeri, /* 40MHz */
.maxMbNum = 64U,
.enableSelfWakeup = true,
.enableIndividMask = true,
.enableCANFD = false,
BAUDRATE_250k,
.enableLBUFTransmittedFirst = true
};
const flexcan_config_t can_3_config = {
.clkSrc = FLEXCAN_ClkSrcPeri, /* 40MHz */
.maxMbNum = 64U,
.enableSelfWakeup = true,
.enableIndividMask = true,
.enableCANFD = false,
BAUDRATE_250k,
.enableLBUFTransmittedFirst = true
};
const flexcan_config_t can_4_config = {
.clkSrc = FLEXCAN_ClkSrcPeri, /* 40MHz */
.maxMbNum = 64U,
.enableSelfWakeup = true,
.enableIndividMask = true,
.enableCANFD = false,
BAUDRATE_1M_5M,
.enableLBUFTransmittedFirst = true
};
const flexcan_config_t can_5_config = {
.clkSrc = FLEXCAN_ClkSrcPeri, /* 40MHz */
.maxMbNum = 64U,
.enableSelfWakeup = true,
.enableIndividMask = true,
.enableCANFD = false,
BAUDRATE_250k,
.enableLBUFTransmittedFirst = true
};
const flexcan_config_t can_6_config = {
.clkSrc = FLEXCAN_ClkSrcPeri, /* 40MHz */
.maxMbNum = 64U,
.enableSelfWakeup = true,
.enableIndividMask = true,
.enableCANFD = false,
BAUDRATE_1M_5M,
.enableLBUFTransmittedFirst = true
};
const flexcan_config_t can_7_config = {
.clkSrc = FLEXCAN_ClkSrcPeri, /* 40MHz */
.maxMbNum = 64U,
.enableSelfWakeup = true,
.enableIndividMask = true,
.enableCANFD = false,
BAUDRATE_250k,
.enableLBUFTransmittedFirst = true
};
static flexcan_rx_fifo_filter_table_t flexcan_tableID[RX_FIFO_ID_FILTER_NUM] = {
{
MAKE_TYPE_A_FILTER(0x1, STANDARD_DATA_ID),//<2F><><EFBFBD><EFBFBD>boot<6F><74><EFBFBD>ص<EFBFBD>ID
MAKE_TYPE_A_FILTER(0x7FF, STANDARD_DATA_ID)
},
{
MAKE_TYPE_A_FILTER(0x3, STANDARD_DATA_ID),//<2F><><EFBFBD><EFBFBD>boot<6F><74><EFBFBD>ص<EFBFBD>ID
MAKE_TYPE_A_FILTER(0x7FF, STANDARD_DATA_ID)
},
{
MAKE_TYPE_A_FILTER(MOTOR_INPUT_ID_1, STANDARD_DATA_ID),
MAKE_TYPE_A_FILTER(0x7FF, STANDARD_DATA_ID)
},
{
MAKE_TYPE_A_FILTER(MOTOR_INPUT_ID_2, STANDARD_DATA_ID),
MAKE_TYPE_A_FILTER(0x7FF, STANDARD_DATA_ID)
},
{
MAKE_TYPE_A_FILTER(0x100, STANDARD_DATA_ID),
MAKE_TYPE_A_FILTER(0x7FF, STANDARD_DATA_ID)
},
{
MAKE_TYPE_A_FILTER(0x100, STANDARD_DATA_ID),
MAKE_TYPE_A_FILTER(0x7FF, STANDARD_DATA_ID)
},
{
MAKE_TYPE_A_FILTER(0x100, STANDARD_DATA_ID),
MAKE_TYPE_A_FILTER(0x7FF, STANDARD_DATA_ID)
},
{
MAKE_TYPE_A_FILTER(0x100, STANDARD_DATA_ID),
MAKE_TYPE_A_FILTER(0x7FF, STANDARD_DATA_ID)
},
{
MAKE_TYPE_A_FILTER(0x100, STANDARD_DATA_ID),
MAKE_TYPE_A_FILTER(0x7FF, STANDARD_DATA_ID)
},
{
MAKE_TYPE_A_FILTER(0x100, STANDARD_DATA_ID),
MAKE_TYPE_A_FILTER(0x7FF, STANDARD_DATA_ID)
},
{
MAKE_TYPE_A_FILTER(0x100, STANDARD_DATA_ID),
MAKE_TYPE_A_FILTER(0x7FF, STANDARD_DATA_ID)
},
{ /* LSB can be 0 or 1 */
MAKE_TYPE_A_FILTER(0x10C, STANDARD_DATA_ID),
MAKE_TYPE_A_FILTER(0x7FE, STANDARD_DATA_ID)
},
{
MAKE_TYPE_A_FILTER(0x12000023, EXTENDED_DATA_ID),
MAKE_TYPE_A_FILTER(0x1FFFFFFF, EXTENDED_DATA_ID)
},
{ /* LSB can be 0 or 1 */
MAKE_TYPE_A_FILTER(REMOTE_ID_1, EXTENDED_DATA_ID),
MAKE_TYPE_A_FILTER(0x1FFFFFFE, EXTENDED_DATA_ID)
},
/* remaining elements can only be affected by RXFGMASK. */
{
MAKE_TYPE_A_FILTER(0x100, STANDARD_DATA_ID),
MAKE_TYPE_A_FILTER(0x7FF, STANDARD_DATA_ID)
},
{
MAKE_TYPE_A_FILTER(0x100, STANDARD_DATA_ID),
MAKE_TYPE_A_FILTER(0x7FF, STANDARD_DATA_ID)
},
{
MAKE_TYPE_A_FILTER(0x527, STANDARD_DATA_ID),
MAKE_TYPE_A_FILTER(0x7FF, STANDARD_DATA_ID)
},
{
MAKE_TYPE_A_FILTER(0x537, STANDARD_DATA_ID),
MAKE_TYPE_A_FILTER(0x7FF, STANDARD_DATA_ID)
},
{
MAKE_TYPE_A_FILTER(0x547, STANDARD_DATA_ID),
MAKE_TYPE_A_FILTER(0x7FF, STANDARD_DATA_ID)
},
{
MAKE_TYPE_A_FILTER(0x557, STANDARD_DATA_ID),
MAKE_TYPE_A_FILTER(0x7FF, STANDARD_DATA_ID)
},
{
MAKE_TYPE_A_FILTER(0x567, STANDARD_DATA_ID),
MAKE_TYPE_A_FILTER(0x7FF, STANDARD_DATA_ID)
},
{
MAKE_TYPE_A_FILTER(0x577, STANDARD_DATA_ID),
MAKE_TYPE_A_FILTER(0x7FF, STANDARD_DATA_ID)
},
{
MAKE_TYPE_A_FILTER(0x587, STANDARD_DATA_ID),
MAKE_TYPE_A_FILTER(0x7FE, STANDARD_DATA_ID)
},
{
MAKE_TYPE_A_FILTER(0x701, STANDARD_DATA_ID),
MAKE_TYPE_A_FILTER(0x7FE, STANDARD_DATA_ID)
},
{
MAKE_TYPE_A_FILTER(0x12000033, EXTENDED_DATA_ID),
MAKE_TYPE_A_FILTER(0x1FFFFFFF, EXTENDED_DATA_ID)
},
{
MAKE_TYPE_A_FILTER(BMS_INPUT_ID1, EXTENDED_DATA_ID),
MAKE_TYPE_A_FILTER(0x1FFFFFFF, EXTENDED_DATA_ID)
},
{
MAKE_TYPE_A_FILTER(TEMP_MODULE_INPUT_ID_1, EXTENDED_DATA_ID),
MAKE_TYPE_A_FILTER(0x1FFFFFFF, EXTENDED_DATA_ID)
},
{
MAKE_TYPE_A_FILTER(0x12000053, EXTENDED_DATA_ID),
MAKE_TYPE_A_FILTER(0x1FFFFFFF, EXTENDED_DATA_ID)
},
{
MAKE_TYPE_A_FILTER(0x100, EXTENDED_DATA_ID),
MAKE_TYPE_A_FILTER(0x1FFFFFFF, EXTENDED_DATA_ID)
},
{
MAKE_TYPE_A_FILTER(0x100, EXTENDED_DATA_ID),
MAKE_TYPE_A_FILTER(0x1FFFFFFF, EXTENDED_DATA_ID)
},
{
MAKE_TYPE_A_FILTER(0x100, EXTENDED_DATA_ID),
MAKE_TYPE_A_FILTER(0x1FFFFFFF, EXTENDED_DATA_ID)
},
{
MAKE_TYPE_A_FILTER(MOTOR_INPUT_ID_8, EXTENDED_DATA_ID),
MAKE_TYPE_A_FILTER(0x1FFFFFFF, EXTENDED_DATA_ID)
}
};
flexcan_rx_fifo_config_t flexcan_fifo_cfg = {
.priority = FLEXCAN_RxFifoPrioHigh,
.idFilterType = FLEXCAN_RxFifoFilterTypeA,
.idFilterNum = RX_FIFO_ID_FILTER_NUM,
.filter_tab = &flexcan_tableID[0]
};
flexcan_rx_fifo_config_t can_0_fifo_config = {
.priority = FLEXCAN_RxFifoPrioHigh,
.idFilterType = FLEXCAN_RxFifoFilterTypeA,
.idFilterNum = RX_FIFO_ID_FILTER_NUM,
.filter_tab = &flexcan_tableID[0]
};
flexcan_rx_fifo_config_t can_1_fifo_config = {
.priority = FLEXCAN_RxFifoPrioHigh,
.idFilterType = FLEXCAN_RxFifoFilterTypeA,
.idFilterNum = RX_FIFO_ID_FILTER_NUM,
.filter_tab = &flexcan_tableID[0]
};
flexcan_rx_fifo_config_t can_2_fifo_config = {
.priority = FLEXCAN_RxFifoPrioHigh,
.idFilterType = FLEXCAN_RxFifoFilterTypeA,
.idFilterNum = RX_FIFO_ID_FILTER_NUM,
.filter_tab = &flexcan_tableID[0]
};
flexcan_rx_fifo_config_t can_3_fifo_config = {
.priority = FLEXCAN_RxFifoPrioHigh,
.idFilterType = FLEXCAN_RxFifoFilterTypeA,
.idFilterNum = RX_FIFO_ID_FILTER_NUM,
.filter_tab = &flexcan_tableID[0]
};
flexcan_rx_fifo_config_t can_4_fifo_config = {
.priority = FLEXCAN_RxFifoPrioHigh,
.idFilterType = FLEXCAN_RxFifoFilterTypeA,
.idFilterNum = RX_FIFO_ID_FILTER_NUM,
.filter_tab = &flexcan_tableID[0]
};
flexcan_rx_fifo_config_t can_5_fifo_config = {
.priority = FLEXCAN_RxFifoPrioHigh,
.idFilterType = FLEXCAN_RxFifoFilterTypeA,
.idFilterNum = RX_FIFO_ID_FILTER_NUM,
.filter_tab = &flexcan_tableID[0]
};
flexcan_rx_fifo_config_t can_6_fifo_config = {
.priority = FLEXCAN_RxFifoPrioHigh,
.idFilterType = FLEXCAN_RxFifoFilterTypeA,
.idFilterNum = RX_FIFO_ID_FILTER_NUM,
.filter_tab = &flexcan_tableID[0]
};
flexcan_rx_fifo_config_t can_7_fifo_config = {
.priority = FLEXCAN_RxFifoPrioHigh,
.idFilterType = FLEXCAN_RxFifoFilterTypeA,
.idFilterNum = RX_FIFO_ID_FILTER_NUM,
.filter_tab = &flexcan_tableID[0]
};

123
boards/e3_176_ref/app_demo/eth-xip/sf/configs/flexcan_cfg.h Normal file
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#ifndef SDRV_FLEXCAN_CFG_H_
#define SDRV_FLEXCAN_CFG_H_
#include <sdrv_flexcan.h>
/* for 40MHz. */
#define BAUDRATE_1M_5M \
.nominalBitTiming = \
{/* 1Mbps, sample point 80% */ \
.preDivider = 1U, \
.rJumpwidth = 5U, \
.propSeg = 10U, \
.phaseSeg1 = 21U, \
.phaseSeg2 = 8U}, \
.dataBitTiming = \
{/* 5Mbps, sample point 75% */ \
.preDivider = \
1U, /* Should be the same as nominalBitTiming.preDivider. */ \
.rJumpwidth = 1U, \
.propSeg = 2U, \
.phaseSeg1 = 3U, \
.phaseSeg2 = 2U}
/* for 40MHz. */
#define BAUDRATE_500K_1M \
.nominalBitTiming = \
{/* 500kbps, sample point 75% */ \
.preDivider = 4U, \
.rJumpwidth = 2U, \
.propSeg = 6U, \
.phaseSeg1 = 8U, \
.phaseSeg2 = 5U}, \
.dataBitTiming = \
{/* 1Mbps, sample point 80% */ \
.preDivider = \
4U, /* Should be the same as nominalBitTiming.preDivider. */ \
.rJumpwidth = 2U, \
.propSeg = 3U, \
.phaseSeg1 = 4U, \
.phaseSeg2 = 2U}
/* for 40MHz. */
#define BAUDRATE_250k \
.nominalBitTiming = \
{/* 500kbps, sample point 75% */ \
.preDivider = 8U, \
.rJumpwidth = 2U, \
.propSeg = 6U, \
.phaseSeg1 = 8U, \
.phaseSeg2 = 5U}, \
.dataBitTiming = \
{/* 1Mbps, sample point 80% */ \
.preDivider = \
4U, /* Should be the same as nominalBitTiming.preDivider. */ \
.rJumpwidth = 2U, \
.propSeg = 3U, \
.phaseSeg1 = 4U, \
.phaseSeg2 = 2U}
#define BAUDRATE_100k \
.nominalBitTiming = \
{/* 1Mbps, sample point 80% */ \
.preDivider = 10U, \
.rJumpwidth = 5U, \
.propSeg = 10U, \
.phaseSeg1 = 21U, \
.phaseSeg2 = 8U}, \
.dataBitTiming = \
{/* 5Mbps, sample point 75% */ \
.preDivider = \
1U, /* Should be the same as nominalBitTiming.preDivider. */ \
.rJumpwidth = 1U, \
.propSeg = 2U, \
.phaseSeg1 = 3U, \
.phaseSeg2 = 2U}
#define RX_FIFO_ID_FILTER_NUM 32
#define USED_MB_FOR_FIFO 14
#define TX_MAILBOX_NUM 7
extern const flexcan_config_t g_flexcan_config;
extern flexcan_rx_fifo_config_t flexcan_fifo_cfg;
extern const flexcan_config_t can_0_config;
extern const flexcan_config_t can_1_config;
extern const flexcan_config_t can_2_config;
extern const flexcan_config_t can_3_config;
extern const flexcan_config_t can_4_config;
extern const flexcan_config_t can_5_config;
extern const flexcan_config_t can_6_config;
extern const flexcan_config_t can_7_config;
extern flexcan_rx_fifo_config_t can_0_fifo_config;
extern flexcan_rx_fifo_config_t can_1_fifo_config;
extern flexcan_rx_fifo_config_t can_2_fifo_config;
extern flexcan_rx_fifo_config_t can_3_fifo_config;
extern flexcan_rx_fifo_config_t can_4_fifo_config;
extern flexcan_rx_fifo_config_t can_5_fifo_config;
extern flexcan_rx_fifo_config_t can_6_fifo_config;
extern flexcan_rx_fifo_config_t can_7_fifo_config;
void flexcan_transfer_callback(flexcan_handle_t *handle,
flexcan_status_e status, uint32_t result,
void *userData);
#endif /* SDRV_FLEXCAN_CFG_H_ */

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boards/e3_176_ref/app_demo/eth-xip/sf/configs/pinmux_cfg.c Normal file
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//*****************************************************************************
//
// WARNING: Automatically generated file, don't modify anymore!!!
//
// Copyright (c) 2021-2029 Semidrive Incorporated. All rights reserved.
// Software License Agreement
//
//*****************************************************************************
#include "pinmux_cfg.h"
#include "interface_24c02.h"
const pin_settings_config_t g_pin_init_config[NUM_OF_CONFIGURED_PINS] = {
/* Pin 23, GPIO_A8, Mux:UART12.TXD */
{
.pin_index = GPIO_A14,//GPIO_A8
.mux = PIN_MUX_ALT4,
.open_drain = PIN_PUSH_PULL,
.pull_config = PIN_PULL_UP,
.drive_strength = PIN_DS_8MA,
.slew_rate = PIN_SR_FAST,
.input_select = PIN_IS_CMOS,
.data_direction = PIN_OUTPUT_DIRECTION,
.interrupt_config = PIN_INTERRUPT_DISABLED,
.initial_value = PIN_LEVEL_LOW,
.force_input = PIN_FORCE_INPUT_NORMAL,
.mode_select = PIN_MODE_DIGITAL,
},
/* Pin 56, GPIO_A9, Mux:UART12.RXD */
{
.pin_index = GPIO_A15,//GPIO_A9
.mux = PIN_MUX_ALT4,
.open_drain = PIN_PUSH_PULL,
.pull_config = PIN_PULL_UP,
.drive_strength = PIN_DS_8MA,
.slew_rate = PIN_SR_FAST,
.input_select = PIN_IS_CMOS_SCHMITT,
.data_direction = PIN_OUTPUT_DIRECTION,
.interrupt_config = PIN_INTERRUPT_DISABLED,
.initial_value = PIN_LEVEL_LOW,
.force_input = PIN_FORCE_INPUT_NORMAL,
.mode_select = PIN_MODE_DIGITAL,
},
/* Pin 23, GPIO_E0, Mux:UART2.TXD */
{
.pin_index = GPIO_E0,//
.mux = PIN_MUX_ALT5,
.open_drain = PIN_PUSH_PULL,
.pull_config = PIN_PULL_UP,
.drive_strength = PIN_DS_8MA,
.slew_rate = PIN_SR_FAST,
.input_select = PIN_IS_CMOS,
.data_direction = PIN_OUTPUT_DIRECTION,
.interrupt_config = PIN_INTERRUPT_DISABLED,
.initial_value = PIN_LEVEL_LOW,
.force_input = PIN_FORCE_INPUT_NORMAL,
.mode_select = PIN_MODE_DIGITAL,
},
/* Pin 24, GPIO_E1, Mux:UART2.RXD */
{
.pin_index = GPIO_E1,//
.mux = PIN_MUX_ALT5,
.open_drain = PIN_PUSH_PULL,
.pull_config = PIN_PULL_UP,
.drive_strength = PIN_DS_8MA,
.slew_rate = PIN_SR_FAST,
.input_select = PIN_IS_CMOS_SCHMITT,
.data_direction = PIN_OUTPUT_DIRECTION,
.interrupt_config = PIN_INTERRUPT_DISABLED,
.initial_value = PIN_LEVEL_LOW,
.force_input = PIN_FORCE_INPUT_NORMAL,
.mode_select = PIN_MODE_DIGITAL,
},
/* Pin 24, GPIO_B10, Mux:UART3.RXD */
{
.pin_index = GPIO_B10,
.mux = PIN_MUX_ALT4,
.open_drain = PIN_PUSH_PULL,
.pull_config = PIN_PULL_UP,
.drive_strength = PIN_DS_8MA,
.slew_rate = PIN_SR_FAST,
.input_select = PIN_IS_CMOS_SCHMITT,
.data_direction = PIN_OUTPUT_DIRECTION,
.interrupt_config = PIN_INTERRUPT_DISABLED,
.initial_value = PIN_LEVEL_LOW,
.force_input = PIN_FORCE_INPUT_NORMAL,
.mode_select = PIN_MODE_DIGITAL,
},
/* Pin 55, GPIO_B11, Mux:UART3.TXD */
{
.pin_index = GPIO_B11,
.mux = PIN_MUX_ALT4,
.open_drain = PIN_PUSH_PULL,
.pull_config = PIN_PULL_UP,
.drive_strength = PIN_DS_8MA,
.slew_rate = PIN_SR_FAST,
.input_select = PIN_IS_CMOS,
.data_direction = PIN_OUTPUT_DIRECTION,
.interrupt_config = PIN_INTERRUPT_DISABLED,
.initial_value = PIN_LEVEL_LOW,
.force_input = PIN_FORCE_INPUT_NORMAL,
.mode_select = PIN_MODE_DIGITAL,
},
/* Pin 23, GPIO_A6, Mux:gpio in */
{
.pin_index = GPIO_A4,
.mux = PIN_MUX_ALT0,
.open_drain = PIN_PUSH_PULL,
.pull_config = PIN_NOPULL,
.drive_strength = PIN_DS_8MA,
.slew_rate = PIN_SR_FAST,
.input_select = PIN_IS_CMOS_SCHMITT,
.data_direction = PIN_INPUT_DIRECTION,
.interrupt_config = PIN_INTERRUPT_DISABLED,
.initial_value = PIN_LEVEL_LOW,
.force_input = PIN_FORCE_INPUT_NORMAL,
.mode_select = PIN_MODE_DIGITAL,
},
/* Pin 23, GPIO_A7, Mux:gpio in */
{
.pin_index = GPIO_C7,
.mux = PIN_MUX_ALT0,
.open_drain = PIN_PUSH_PULL,
.pull_config = PIN_NOPULL,
.drive_strength = PIN_DS_8MA,
.slew_rate = PIN_SR_FAST,
.input_select = PIN_IS_CMOS_SCHMITT,
.data_direction = PIN_INPUT_DIRECTION,
.interrupt_config = PIN_INTERRUPT_DISABLED,
.initial_value = PIN_LEVEL_LOW,
.force_input = PIN_FORCE_INPUT_NORMAL,
.mode_select = PIN_MODE_DIGITAL,
},
/* Pin 38, GPIO_X11, Mux:GPIO_SAFETY.IO38 */
{
.pin_index = GPIO_X11,
.mux = PIN_MUX_ALT0,
.open_drain = PIN_PUSH_PULL,
.pull_config = PIN_NOPULL,
.drive_strength = PIN_DS_8MA,
.slew_rate = PIN_SR_FAST,
.input_select = PIN_IS_CMOS,
.data_direction = PIN_OUTPUT_DIRECTION,
.interrupt_config = PIN_INTERRUPT_DISABLED,
.initial_value = PIN_LEVEL_LOW,
.force_input = PIN_FORCE_INPUT_NORMAL,
.mode_select = PIN_MODE_DIGITAL,
},
/* Pin 38, GPIO_B9, Mux:GPIO_SAFETY.IO38 */
{
.pin_index = GPIO_B9,
.mux = PIN_MUX_ALT0,
.open_drain = PIN_PUSH_PULL,
.pull_config = PIN_NOPULL,
.drive_strength = PIN_DS_8MA,
.slew_rate = PIN_SR_FAST,
.input_select = PIN_IS_CMOS,
.data_direction = PIN_OUTPUT_DIRECTION,
.interrupt_config = PIN_INTERRUPT_DISABLED,
.initial_value = PIN_LEVEL_LOW,
.force_input = PIN_FORCE_INPUT_NORMAL,
.mode_select = PIN_MODE_DIGITAL,
},
/* Pin 77, GPIO_G0, Mux:GPIO_SAFETY.IO77 */
{
.pin_index = GPIO_G0,
.mux = PIN_MUX_ALT0,
.open_drain = PIN_PUSH_PULL,
.pull_config = PIN_PULL_DOWN,
.drive_strength = PIN_DS_8MA,
.slew_rate = PIN_SR_FAST,
.input_select = PIN_IS_CMOS,
.data_direction = PIN_OUTPUT_DIRECTION,
.interrupt_config = PIN_INTERRUPT_DISABLED,
.initial_value = PIN_LEVEL_HIGH,
.force_input = PIN_FORCE_INPUT_NORMAL,
.mode_select = PIN_MODE_DIGITAL,
},
/* Pin 33, GPIO_L4, Mux:CANFD3.RX */
{
.pin_index = GPIO_L4,
.mux = PIN_MUX_ALT3,
.open_drain = PIN_PUSH_PULL,
.pull_config = PIN_NOPULL,
.drive_strength = PIN_DS_8MA,
.slew_rate = PIN_SR_SLOW,
.input_select = PIN_IS_CMOS_SCHMITT,
.data_direction = PIN_OUTPUT_DIRECTION,
.interrupt_config = PIN_INTERRUPT_DISABLED,
.initial_value = PIN_LEVEL_LOW,
.force_input = PIN_FORCE_INPUT_NORMAL,
.mode_select = PIN_MODE_DIGITAL,
},
/* Pin 34, GPIO_L5, Mux:CANFD3.TX */
{
.pin_index = GPIO_L5,
.mux = PIN_MUX_ALT3,
.open_drain = PIN_PUSH_PULL,
.pull_config = PIN_NOPULL,
.drive_strength = PIN_DS_8MA,
.slew_rate = PIN_SR_SLOW,
.input_select = PIN_IS_CMOS,
.data_direction = PIN_OUTPUT_DIRECTION,
.interrupt_config = PIN_INTERRUPT_DISABLED,
.initial_value = PIN_LEVEL_LOW,
.force_input = PIN_FORCE_INPUT_NORMAL,
.mode_select = PIN_MODE_DIGITAL,
},
/* Pin 103, GPIO_F0, Mux:CANFD7.RX */
{
.pin_index = GPIO_F0,
.mux = PIN_MUX_ALT1,
.open_drain = PIN_PUSH_PULL,
.pull_config = PIN_NOPULL,
.drive_strength = PIN_DS_8MA,
.slew_rate = PIN_SR_SLOW,
.input_select = PIN_IS_CMOS_SCHMITT,
.data_direction = PIN_OUTPUT_DIRECTION,
.interrupt_config = PIN_INTERRUPT_DISABLED,
.initial_value = PIN_LEVEL_LOW,
.force_input = PIN_FORCE_INPUT_NORMAL,
.mode_select = PIN_MODE_DIGITAL,
},
/* Pin 104, GPIO_F1, Mux:CANFD7.TX */
{
.pin_index = GPIO_F1,
.mux = PIN_MUX_ALT1,
.open_drain = PIN_PUSH_PULL,
.pull_config = PIN_NOPULL,
.drive_strength = PIN_DS_8MA,
.slew_rate = PIN_SR_SLOW,
.input_select = PIN_IS_CMOS,
.data_direction = PIN_OUTPUT_DIRECTION,
.interrupt_config = PIN_INTERRUPT_DISABLED,
.initial_value = PIN_LEVEL_LOW,
.force_input = PIN_FORCE_INPUT_NORMAL,
.mode_select = PIN_MODE_DIGITAL,
},
/* Pin 109, GPIO_L0, Mux:CANFD23.RX */
{
.pin_index = GPIO_L0,
.mux = PIN_MUX_ALT3,
.open_drain = PIN_PUSH_PULL,
.pull_config = PIN_NOPULL,
.drive_strength = PIN_DS_8MA,
.slew_rate = PIN_SR_SLOW,
.input_select = PIN_IS_CMOS_SCHMITT,
.data_direction = PIN_OUTPUT_DIRECTION,
.interrupt_config = PIN_INTERRUPT_DISABLED,
.initial_value = PIN_LEVEL_LOW,
.force_input = PIN_FORCE_INPUT_NORMAL,
.mode_select = PIN_MODE_DIGITAL,
},
/* Pin 110, GPIO_L1, Mux:CANFD23.TX */
{
.pin_index = GPIO_L1,
.mux = PIN_MUX_ALT3,
.open_drain = PIN_PUSH_PULL,
.pull_config = PIN_NOPULL,
.drive_strength = PIN_DS_8MA,
.slew_rate = PIN_SR_SLOW,
.input_select = PIN_IS_CMOS,
.data_direction = PIN_OUTPUT_DIRECTION,
.interrupt_config = PIN_INTERRUPT_DISABLED,
.initial_value = PIN_LEVEL_LOW,
.force_input = PIN_FORCE_INPUT_NORMAL,
.mode_select = PIN_MODE_DIGITAL,
},
/* Pin 111, GPIO_L2, Mux:CANFD21.RX */
{
.pin_index = GPIO_L2,
.mux = PIN_MUX_ALT3,
.open_drain = PIN_PUSH_PULL,
.pull_config = PIN_NOPULL,
.drive_strength = PIN_DS_8MA,
.slew_rate = PIN_SR_SLOW,
.input_select = PIN_IS_CMOS_SCHMITT,
.data_direction = PIN_OUTPUT_DIRECTION,
.interrupt_config = PIN_INTERRUPT_DISABLED,
.initial_value = PIN_LEVEL_LOW,
.force_input = PIN_FORCE_INPUT_NORMAL,
.mode_select = PIN_MODE_DIGITAL,
},
/* Pin 112, GPIO_L3, Mux:CANFD21.TX */
{
.pin_index = GPIO_L3,
.mux = PIN_MUX_ALT3,
.open_drain = PIN_PUSH_PULL,
.pull_config = PIN_NOPULL,
.drive_strength = PIN_DS_8MA,
.slew_rate = PIN_SR_SLOW,
.input_select = PIN_IS_CMOS,
.data_direction = PIN_OUTPUT_DIRECTION,
.interrupt_config = PIN_INTERRUPT_DISABLED,
.initial_value = PIN_LEVEL_LOW,
.force_input = PIN_FORCE_INPUT_NORMAL,
.mode_select = PIN_MODE_DIGITAL,
},
/* Pin 115, GPIO_L6, Mux:CANFD4.RX */
{
.pin_index = GPIO_L6,
.mux = PIN_MUX_ALT3,
.open_drain = PIN_PUSH_PULL,
.pull_config = PIN_NOPULL,
.drive_strength = PIN_DS_8MA,
.slew_rate = PIN_SR_SLOW,
.input_select = PIN_IS_CMOS_SCHMITT,
.data_direction = PIN_OUTPUT_DIRECTION,
.interrupt_config = PIN_INTERRUPT_DISABLED,
.initial_value = PIN_LEVEL_LOW,
.force_input = PIN_FORCE_INPUT_NORMAL,
.mode_select = PIN_MODE_DIGITAL,
},
/* Pin 116, GPIO_L7, Mux:CANFD4.TX */
{
.pin_index = GPIO_L7,
.mux = PIN_MUX_ALT3,
.open_drain = PIN_PUSH_PULL,
.pull_config = PIN_NOPULL,
.drive_strength = PIN_DS_8MA,
.slew_rate = PIN_SR_SLOW,
.input_select = PIN_IS_CMOS,
.data_direction = PIN_OUTPUT_DIRECTION,
.interrupt_config = PIN_INTERRUPT_DISABLED,
.initial_value = PIN_LEVEL_LOW,
.force_input = PIN_FORCE_INPUT_NORMAL,
.mode_select = PIN_MODE_DIGITAL,
},
/* Pin 117, GPIO_L8, Mux:CANFD5.RX */
{
.pin_index = GPIO_L8,
.mux = PIN_MUX_ALT2,
.open_drain = PIN_PUSH_PULL,
.pull_config = PIN_NOPULL,
.drive_strength = PIN_DS_8MA,
.slew_rate = PIN_SR_SLOW,
.input_select = PIN_IS_CMOS_SCHMITT,
.data_direction = PIN_OUTPUT_DIRECTION,
.interrupt_config = PIN_INTERRUPT_DISABLED,
.initial_value = PIN_LEVEL_LOW,
.force_input = PIN_FORCE_INPUT_NORMAL,
.mode_select = PIN_MODE_DIGITAL,
},
/* Pin 118, GPIO_L9, Mux:CANFD5.TX */
{
.pin_index = GPIO_L9,
.mux = PIN_MUX_ALT2,
.open_drain = PIN_PUSH_PULL,
.pull_config = PIN_NOPULL,
.drive_strength = PIN_DS_8MA,
.slew_rate = PIN_SR_SLOW,
.input_select = PIN_IS_CMOS,
.data_direction = PIN_OUTPUT_DIRECTION,
.interrupt_config = PIN_INTERRUPT_DISABLED,
.initial_value = PIN_LEVEL_LOW,
.force_input = PIN_FORCE_INPUT_NORMAL,
.mode_select = PIN_MODE_DIGITAL,
},
/* Pin 105, GPIO_F2, Mux:CANFD16.RX */
{
.pin_index = GPIO_F2,
.mux = PIN_MUX_ALT1,
.open_drain = PIN_PUSH_PULL,
.pull_config = PIN_NOPULL,
.drive_strength = PIN_DS_8MA,
.slew_rate = PIN_SR_SLOW,
.input_select = PIN_IS_CMOS_SCHMITT,
.data_direction = PIN_OUTPUT_DIRECTION,
.interrupt_config = PIN_INTERRUPT_DISABLED,
.initial_value = PIN_LEVEL_LOW,
.force_input = PIN_FORCE_INPUT_NORMAL,
.mode_select = PIN_MODE_DIGITAL,
},
/* Pin 106, GPIO_F3, Mux:CANFD16.TX */
{
.pin_index = GPIO_F3,
.mux = PIN_MUX_ALT1,
.open_drain = PIN_PUSH_PULL,
.pull_config = PIN_NOPULL,
.drive_strength = PIN_DS_8MA,
.slew_rate = PIN_SR_SLOW,
.input_select = PIN_IS_CMOS,
.data_direction = PIN_OUTPUT_DIRECTION,
.interrupt_config = PIN_INTERRUPT_DISABLED,
.initial_value = PIN_LEVEL_LOW,
.force_input = PIN_FORCE_INPUT_NORMAL,
.mode_select = PIN_MODE_DIGITAL,
},
/* Pin 38, GPIO_F5, Mux:GPIO_SAFETY.IO39 */
{
.pin_index = GPIO_F5,
.mux = PIN_MUX_ALT0,
.open_drain = PIN_PUSH_PULL,
.pull_config = PIN_PULL_UP,
.drive_strength = PIN_DS_12MA,
.slew_rate = PIN_SR_FAST,
.input_select = PIN_IS_CMOS,
.data_direction = PIN_OUTPUT_DIRECTION,
.interrupt_config = PIN_INTERRUPT_DISABLED,
.initial_value = PIN_LEVEL_LOW,
.force_input = PIN_FORCE_INPUT_NORMAL,
.mode_select = PIN_MODE_DIGITAL,
},
/* Pin 95, GPIO_H6, Mux:CANFD6.RX */
{
.pin_index = GPIO_H6,
.mux = PIN_MUX_ALT2,
.open_drain = PIN_PUSH_PULL,
.pull_config = PIN_NOPULL,
.drive_strength = PIN_DS_8MA,
.slew_rate = PIN_SR_SLOW,
.input_select = PIN_IS_CMOS_SCHMITT,
.data_direction = PIN_OUTPUT_DIRECTION,
.interrupt_config = PIN_INTERRUPT_DISABLED,
.initial_value = PIN_LEVEL_LOW,
.force_input = PIN_FORCE_INPUT_NORMAL,
.mode_select = PIN_MODE_DIGITAL,
},
/* Pin 96, GPIO_H7, Mux:CANFD6.TX */
{
.pin_index = GPIO_H7,
.mux = PIN_MUX_ALT2,
.open_drain = PIN_PUSH_PULL,
.pull_config = PIN_NOPULL,
.drive_strength = PIN_DS_8MA,
.slew_rate = PIN_SR_SLOW,
.input_select = PIN_IS_CMOS,
.data_direction = PIN_OUTPUT_DIRECTION,
.interrupt_config = PIN_INTERRUPT_DISABLED,
.initial_value = PIN_LEVEL_LOW,
.force_input = PIN_FORCE_INPUT_NORMAL,
.mode_select = PIN_MODE_DIGITAL,
},
/* Pin 38, GPIO_H12, Mux:GPIO_SAFETY.IO38 */
{
.pin_index = GPIO_H12,
.mux = PIN_MUX_ALT0,
.open_drain = PIN_PUSH_PULL,
.pull_config = PIN_NOPULL,
.drive_strength = PIN_DS_8MA,
.slew_rate = PIN_SR_FAST,
.input_select = PIN_IS_CMOS,
.data_direction = PIN_OUTPUT_DIRECTION,
.interrupt_config = PIN_INTERRUPT_DISABLED,
.initial_value = PIN_LEVEL_HIGH,
.force_input = PIN_FORCE_INPUT_NORMAL,
.mode_select = PIN_MODE_DIGITAL,
},
/* Pin 38, GPIO_H13, Mux:GPIO_SAFETY.IO39 */
{
.pin_index = GPIO_H13,
.mux = PIN_MUX_ALT0,
.open_drain = PIN_PUSH_PULL,
.pull_config = PIN_NOPULL,
.drive_strength = PIN_DS_8MA,
.slew_rate = PIN_SR_FAST,
.input_select = PIN_IS_CMOS,
.data_direction = PIN_OUTPUT_DIRECTION,
.interrupt_config = PIN_INTERRUPT_DISABLED,
.initial_value = PIN_LEVEL_HIGH,
.force_input = PIN_FORCE_INPUT_NORMAL,
.mode_select = PIN_MODE_DIGITAL,
},
#if EN_24C02
/* Pin 23, GPIO_Y2, Mux:I2C.SCL */
{
.pin_index = GPIO_Y2,
.mux = PIN_MUX_ALT0,
.open_drain = PIN_PUSH_PULL,
.pull_config = PIN_PULL_UP,
.drive_strength = PIN_DS_8MA,
.slew_rate = PIN_SR_FAST,
.input_select = PIN_IS_CMOS,
.data_direction = PIN_OUTPUT_DIRECTION,
.interrupt_config = PIN_INTERRUPT_DISABLED,
.initial_value = PIN_LEVEL_LOW,
.force_input = PIN_FORCE_INPUT_NORMAL,
.mode_select = PIN_MODE_DIGITAL,
},
/* Pin 24, GPIO_Y3, Mux:I2C.SDA */
{
.pin_index = GPIO_Y3,
.mux = PIN_MUX_ALT0,
.open_drain = PIN_OPEN_DRAIN,
.pull_config = PIN_PULL_UP,
.drive_strength = PIN_DS_8MA,
.slew_rate = PIN_SR_FAST,
.input_select = PIN_IS_CMOS,
.data_direction = PIN_OUTPUT_DIRECTION,
.interrupt_config = PIN_INTERRUPT_DISABLED,
.initial_value = PIN_LEVEL_LOW,
.force_input = PIN_FORCE_INPUT_NORMAL,
.mode_select = PIN_MODE_DIGITAL,
},
/* Pin 24, GPIO_Y1, Mux:I2C.WP */
{
.pin_index = GPIO_Y1,
.mux = PIN_MUX_ALT0,
.open_drain = PIN_PUSH_PULL,
.pull_config = PIN_PULL_UP,
.drive_strength = PIN_DS_8MA,
.slew_rate = PIN_SR_FAST,
.input_select = PIN_IS_CMOS,
.data_direction = PIN_OUTPUT_DIRECTION,
.interrupt_config = PIN_INTERRUPT_DISABLED,
.initial_value = PIN_LEVEL_LOW,
.force_input = PIN_FORCE_INPUT_NORMAL,
.mode_select = PIN_MODE_DIGITAL,
},
#else
/* PortPinid: 0 - SPI6_SS0 */
{
.pin_index = GPIO_Y2,
.mux = PIN_MUX_ALT3,
.open_drain = PIN_PUSH_PULL,
.pull_config = PIN_NOPULL,
.drive_strength = PIN_DS_8MA,
.slew_rate = PIN_SR_FAST,
.input_select = PIN_IS_CMOS,
.data_direction = PIN_OUTPUT_DIRECTION,
.interrupt_config = PIN_INTERRUPT_DISABLED,
.initial_value = PIN_LEVEL_LOW,
.force_input = PIN_FORCE_INPUT_NORMAL,
.mode_select = PIN_MODE_DIGITAL,
},
/* PortPinid: 1 - SPI6_SCLK */
{
.pin_index = GPIO_Y3,
.mux = PIN_MUX_ALT3,
.open_drain = PIN_PUSH_PULL,
.pull_config = PIN_PULL_UP,
.drive_strength = PIN_DS_8MA,
.slew_rate = PIN_SR_FAST,
.input_select = PIN_IS_CMOS,
.data_direction = PIN_OUTPUT_DIRECTION,
.interrupt_config = PIN_INTERRUPT_DISABLED,
.initial_value = PIN_LEVEL_LOW,
.force_input = PIN_FORCE_INPUT_NORMAL,
.mode_select = PIN_MODE_DIGITAL,
},
/* PortPinid: 2 - SPI6_MISO */
{
.pin_index = GPIO_Y4,
.mux = PIN_MUX_ALT3,
.open_drain = PIN_PUSH_PULL,
.pull_config = PIN_PULL_UP,
.drive_strength = PIN_DS_8MA,
.slew_rate = PIN_SR_FAST,
.input_select = PIN_IS_CMOS,
.data_direction = PIN_OUTPUT_DIRECTION,
.interrupt_config = PIN_INTERRUPT_DISABLED,
.initial_value = PIN_LEVEL_LOW,
.force_input = PIN_FORCE_INPUT_NORMAL,
.mode_select = PIN_MODE_DIGITAL,
},
/* PortPinid: 3 - SPI6_MOSI */
{
.pin_index = GPIO_Y5,
.mux = PIN_MUX_ALT3,
.open_drain = PIN_PUSH_PULL,
.pull_config = PIN_PULL_UP,
.drive_strength = PIN_DS_8MA,
.slew_rate = PIN_SR_FAST,
.input_select = PIN_IS_CMOS,
.data_direction = PIN_OUTPUT_DIRECTION,
.interrupt_config = PIN_INTERRUPT_DISABLED,
.initial_value = PIN_LEVEL_HIGH,
.force_input = PIN_FORCE_INPUT_NORMAL,
.mode_select = PIN_MODE_DIGITAL,
},
#endif
/* Pin 78, GPIO_G1, Mux:ETHERNET1.TXD0 */
{
.pin_index = GPIO_G1,
.mux = PIN_MUX_ALT1,
.open_drain = PIN_PUSH_PULL,
.pull_config = PIN_PULL_DOWN,
.drive_strength = PIN_DS_8MA,
.slew_rate = PIN_SR_FAST,
.input_select = PIN_IS_CMOS,
.data_direction = PIN_OUTPUT_DIRECTION,
.interrupt_config = PIN_INTERRUPT_DISABLED,
.initial_value = PIN_LEVEL_LOW,
.force_input = PIN_FORCE_INPUT_NORMAL,
.mode_select = PIN_MODE_DIGITAL,
},
/* Pin 79, GPIO_G2, Mux:ETHERNET1.TXD1 */
{
.pin_index = GPIO_G2,
.mux = PIN_MUX_ALT1,
.open_drain = PIN_PUSH_PULL,
.pull_config = PIN_PULL_DOWN,
.drive_strength = PIN_DS_8MA,
.slew_rate = PIN_SR_FAST,
.input_select = PIN_IS_CMOS,
.data_direction = PIN_OUTPUT_DIRECTION,
.interrupt_config = PIN_INTERRUPT_DISABLED,
.initial_value = PIN_LEVEL_LOW,
.force_input = PIN_FORCE_INPUT_NORMAL,
.mode_select = PIN_MODE_DIGITAL,
},
/* Pin 80, GPIO_G3, Mux:ETHERNET1.MDIO */
{
.pin_index = GPIO_G3,
.mux = PIN_MUX_ALT2,
.open_drain = PIN_PUSH_PULL,
.pull_config = PIN_PULL_DOWN,
.drive_strength = PIN_DS_8MA,
.slew_rate = PIN_SR_FAST,
.input_select = PIN_IS_CMOS,
.data_direction = PIN_OUTPUT_DIRECTION,
.interrupt_config = PIN_INTERRUPT_DISABLED,
.initial_value = PIN_LEVEL_LOW,
.force_input = PIN_FORCE_INPUT_NORMAL,
.mode_select = PIN_MODE_DIGITAL,
},
/* Pin 81, GPIO_G4, Mux:ETHERNET1.MDC */
{
.pin_index = GPIO_G4,
.mux = PIN_MUX_ALT2,
.open_drain = PIN_PUSH_PULL,
.pull_config = PIN_PULL_DOWN,
.drive_strength = PIN_DS_8MA,
.slew_rate = PIN_SR_FAST,
.input_select = PIN_IS_CMOS,
.data_direction = PIN_OUTPUT_DIRECTION,
.interrupt_config = PIN_INTERRUPT_DISABLED,
.initial_value = PIN_LEVEL_LOW,
.force_input = PIN_FORCE_INPUT_NORMAL,
.mode_select = PIN_MODE_DIGITAL,
},
/* Pin 82, GPIO_G5, Mux:ETHERNET1.TXEN */
{
.pin_index = GPIO_G5,
.mux = PIN_MUX_ALT1,
.open_drain = PIN_PUSH_PULL,
.pull_config = PIN_PULL_DOWN,
.drive_strength = PIN_DS_8MA,
.slew_rate = PIN_SR_FAST,
.input_select = PIN_IS_CMOS,
.data_direction = PIN_OUTPUT_DIRECTION,
.interrupt_config = PIN_INTERRUPT_DISABLED,
.initial_value = PIN_LEVEL_LOW,
.force_input = PIN_FORCE_INPUT_NORMAL,
.mode_select = PIN_MODE_DIGITAL,
},
/* Pin 84, GPIO_G7, Mux:ETHERNET1.RXD0 */
{
.pin_index = GPIO_G7,
.mux = PIN_MUX_ALT1,
.open_drain = PIN_PUSH_PULL,
.pull_config = PIN_PULL_DOWN,
.drive_strength = PIN_DS_8MA,
.slew_rate = PIN_SR_FAST,
.input_select = PIN_IS_CMOS_SCHMITT,
.data_direction = PIN_OUTPUT_DIRECTION,
.interrupt_config = PIN_INTERRUPT_DISABLED,
.initial_value = PIN_LEVEL_LOW,
.force_input = PIN_FORCE_INPUT_NORMAL,
.mode_select = PIN_MODE_DIGITAL,
},
/* Pin 85, GPIO_G8, Mux:ETHERNET1.RXD1 */
{
.pin_index = GPIO_G8,
.mux = PIN_MUX_ALT1,
.open_drain = PIN_PUSH_PULL,
.pull_config = PIN_PULL_DOWN,
.drive_strength = PIN_DS_8MA,
.slew_rate = PIN_SR_FAST,
.input_select = PIN_IS_CMOS_SCHMITT,
.data_direction = PIN_OUTPUT_DIRECTION,
.interrupt_config = PIN_INTERRUPT_DISABLED,
.initial_value = PIN_LEVEL_LOW,
.force_input = PIN_FORCE_INPUT_NORMAL,
.mode_select = PIN_MODE_DIGITAL,
},
/* Pin 86, GPIO_G9, Mux:ETHERNET1.RMII_REF_CLK */
{
.pin_index = GPIO_G9,
.mux = PIN_MUX_ALT2,
.open_drain = PIN_PUSH_PULL,
.pull_config = PIN_PULL_DOWN,
.drive_strength = PIN_DS_8MA,
.slew_rate = PIN_SR_FAST,
.input_select = PIN_IS_CMOS_SCHMITT,
.data_direction = PIN_OUTPUT_DIRECTION,
.interrupt_config = PIN_INTERRUPT_DISABLED,
.initial_value = PIN_LEVEL_LOW,
.force_input = PIN_FORCE_INPUT_ENABLE,
.mode_select = PIN_MODE_DIGITAL,
},
/* Pin 87, GPIO_G10, Mux:ETHERNET1.RX_ER */
{
.pin_index = GPIO_G10,
.mux = PIN_MUX_ALT2,
.open_drain = PIN_PUSH_PULL,
.pull_config = PIN_PULL_DOWN,
.drive_strength = PIN_DS_8MA,
.slew_rate = PIN_SR_FAST,
.input_select = PIN_IS_CMOS_SCHMITT,
.data_direction = PIN_OUTPUT_DIRECTION,
.interrupt_config = PIN_INTERRUPT_DISABLED,
.initial_value = PIN_LEVEL_LOW,
.force_input = PIN_FORCE_INPUT_NORMAL,
.mode_select = PIN_MODE_DIGITAL,
},
/* Pin 88, GPIO_G11, Mux:ETHERNET1.RXDV */
{
.pin_index = GPIO_G11,
.mux = PIN_MUX_ALT1,
.open_drain = PIN_PUSH_PULL,
.pull_config = PIN_PULL_DOWN,
.drive_strength = PIN_DS_8MA,
.slew_rate = PIN_SR_FAST,
.input_select = PIN_IS_CMOS_SCHMITT,
.data_direction = PIN_OUTPUT_DIRECTION,
.interrupt_config = PIN_INTERRUPT_DISABLED,
.initial_value = PIN_LEVEL_LOW,
.force_input = PIN_FORCE_INPUT_NORMAL,
.mode_select = PIN_MODE_DIGITAL,
},
};

11
boards/e3_176_ref/app_demo/eth-xip/sf/configs/pinmux_cfg.h Normal file
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@@ -0,0 +1,11 @@
#ifndef SDRV_PINMUX_CFG_H_
#define SDRV_PINMUX_CFG_H_
#include <sdrv_pinctrl.h>
#define NUM_OF_CONFIGURED_PINS 44
extern const pin_settings_config_t g_pin_init_config[NUM_OF_CONFIGURED_PINS];
#endif /* SDRV_PINMUX_CFG_H_ */

17
boards/e3_176_ref/app_demo/eth-xip/sf/configs/reset_cfg.c Normal file
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@@ -0,0 +1,17 @@
#include <reset_ip.h>
#include "reset_cfg.h"
sdrv_rstgen_sig_t *board_reset_array[NUM_OF_RSTGEN_SIGS] = {
&rstsig_enet1,
&rstsig_vic1,
&rstsig_canfd3,
&rstsig_canfd16,
&rstsig_canfd21,
&rstsig_canfd4,
&rstsig_canfd5,
&rstsig_canfd6,
&rstsig_canfd7,
&rstsig_canfd23,
};

11
boards/e3_176_ref/app_demo/eth-xip/sf/configs/reset_cfg.h Normal file
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@@ -0,0 +1,11 @@
#ifndef SDRV_RESET_CFG_H_
#define SDRV_RESET_CFG_H_
#include <sdrv_rstgen.h>
#include <reset_ip.h>
#define NUM_OF_RSTGEN_SIGS 10
extern sdrv_rstgen_sig_t *board_reset_array[NUM_OF_RSTGEN_SIGS];
#endif /* SDRV_RESET_CFG_H_ */

7
boards/e3_176_ref/app_demo/eth-xip/sf/configs/scr_cfg.c Normal file
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@@ -0,0 +1,7 @@
#include <regs_base.h>
#include <scr_cfg.h>
/*scr structures*/
sdrv_scr_t g_scr_ctrl = {
.base = APB_SCR_SF_BASE,
};

4
boards/e3_176_ref/app_demo/eth-xip/sf/configs/scr_cfg.h Normal file
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@@ -0,0 +1,4 @@
#include <sdrv_scr.h>
/*exported scr*/
extern sdrv_scr_t g_scr_ctrl;